DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 7/31/2026. Claims 1-3, 6, 8, 17, 30, and 32 have been amended. No new claims have been added or canceled. Currently, claims 1-8, 11-17, and 30-34 are pending.
Applicant’s amendment to claim 2 successfully overcomes the objection to claim 8 set forth in the previous Office Action.
Applicant’s amendments to claims 17 and 32 successfully overcomes the 112(b) rejection of claim 17, 32, 33, and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments filed 7/31/2026 regarding claims 2-3 and 6 are persuasive. Thus, the 35 U.S.C. § 102(a)(1) rejection of claim 6 and the 35 U.S.C. § 103 rejection of claims 2-3 are withdrawn. After further search, claims 2-3 and 6 are rejected in view of newly found art as set forth in the rejection below. Also note regarding the rejection of claims 2-3 below that a different motivation from Trindade is newly used for the routine-optimization rationale.
Applicant’s arguments with respect to amended claim 1 and its dependent claims (excluding claims 2-3 and 6) have been considered but are moot because the new ground of rejection Jang et al. (US 20230071812) does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments with respect to amended claim 30 are persuasive. After further search and consideration, Jo et al. (US 20250323135) has been found, which teaches the limitations of amended claim 30, as set forth in the rejection below.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, for claim 3, the third component 10 mounted side-by-side with the second component 6 on the first component 5 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-8, 11-17, and 30-34 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, the claim language treats “at least one electrically insulating layer structure” (lines 2-3) of the stack (line 2) as a separate element from “a first electrically insulating filling material” (line 6). This would contradict Applicant’s Fig. 3. According to claim 1, the interface surface (8) of the stack would be located at the surfaces of the at least one electrically insulating layer structure 4 instead of first electrically insulating filling material 40, and the second electrically insulating filling 9 would form an interface with 4 rather than with 40.
It appears from the specification that “a first electrically insulating filling material” should instead become part of the earlier recited “at least one electrically insulating layer structure” that is part of the “stack.” In para. [0063] and Fig. 2 step S1, an initial stack 2 comprising at least one electrically conductive layer structure 3 and at least one electrically insulating layer structure 4 is formed. Then in para. [0075] and Fig. 2 step S4, a first electrically insulating filling material 40 fills in the main cavity 20 (labelled in step S2) and “belongs in its entirety to the at least one electrically insulating layer structure 4.” Thus, if the first electrically insulating filling material 40 becomes one of the “at least one electrically insulating layer structure” 4, this would allow interface surface of the stack 8 (Fig. 3) to be located at the surfaces of 40 instead of 4, and a second electrically insulating filling 9 (Fig. 3) to form an interface with 40 rather than with 4, as required by claim 1.
For the purposes of examination with regard to the prior art, in line 6 of the claim, “a first electrically insulating filling material” will be treated as --the at least one electrically insulating layer structure comprises a first electrically insulating filling material--.
Claims 2-8 and 11-17, because they are dependent on claim 1, inherit the deficiencies of claim 1.
Regarding claim 30, for the same reasons as claim 1, the claim language contradicts Applicant’s Fig. 3.
For the purposes of examination with regard to the prior art, in lines 6-8 of the claim, “a first electrically insulating filling material” will be treated as --the at least one electrically insulating layer structure comprises a first electrically insulating filling material--.
Claims 31-34, because they are dependent on claim 30, inherit the deficiencies of claim 30.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6-8, 12-13, and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jang et al. (US 20230071812).
Regarding claim 1, Jang teaches, in Fig. 6A, a component carrier (1000F, [0061]) comprising:
a stack comprising at least one electrically conductive layer structure (543a/543b, [0064]) and at least one electrically insulating layer structure (520, 551a/551b; [0042], [0062]);
a main cavity (CA, [0062]) provided in the at least one electrically insulating layer structure (551a/551b);
a first component (100, [0026]) placed in the main cavity (CA);
a first electrically insulating filling material (520, [0042]) filling or encapsulating the main cavity (CA) with the placed first component (100), embedding the first component in the stack (543a/543b, 551a/551b, and 520);
a second component (200, [0026]) mounted on the first component (100) and in a cavity (filled by 400, labelled in Figs. 1A-1B) which is delimited by an interface surface of the stack (543a/543b, 551a/551b, and 520); and
a second electrically insulating filling (400, labelled in Figs. 1A-1B, [0025]) which at least partially fills the cavity and extends up to the interface surface and thereby forms an interface with at least one of the at least one electrically insulating layer structure (520) (see Fig. 6A).
Regarding claim 4, Jang further teaches, in Fig. 6A, that an entire bottom of the cavity (filled by 400) is defined by an upper main surface of the first component (100).
Regarding claim 6, Jang further teaches that the first electrically insulating filling material (520) and the at least one electrically insulating layer structure (551a/551b) are made of the same materials ([0042], [0063]).
Regarding claim 7, Jang further teaches, in Fig. 6A, the following:
an electrically conductive adhesive (first upper pad 106 and second lower pad 204) between the first component (100) and the second component (200) ([0037]);
an insulating adhesive (first upper dielectric layer 107 and the second lower dielectric layer 205) between the first component (100) and the second component (200) ([0037]).
Regarding claim 8, Jang further teaches, in Fig. 6A, wherein the first component (100) and the second component (200) are electrically coupled with each other directly via their mutually facing main surfaces by a metallic structure ([0037], first upper pad 106 and second lower pad 204),
wherein at least one of the first component (100) and the second component (200) comprises at least one through via (130 and 230, [0020]) passing through the at least one of the first component and the second component,
wherein the metallic structure (first upper pad 106 and second lower pad 204) is bonding structure, a solder structure or a sinter structure ([0037], bonding structure).
Regarding claim 12, Jang further teaches that at least one of the at least one electrically insulating layer structure (551a/551b) is thermally conductive and comprises a thermal prepreg ([0063]).
Regarding claim 13, Jang further teaches that at least one of the first component (100) and the second component (200) is an electronic component ([0026], both are semiconductor chips).
Regarding claim 16, Jang further teaches, in Fig. 6A, that the first component (100) has a larger main (top) surface than the second component (200).
Regarding claim 17, Jang further teaches, in Fig. 6A, that a height of the cavity (filled by 400) along a stack thickness is greater than a height of the second component (200) mounted in the cavity.
Claims 1, 5, 14, 30-31, and 34 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jo et al. (US 20250323135).
Regarding claim 1, Jo teaches, in Fig. 12, a component carrier ([0052]) comprising:
a stack (layers 124 through 160) comprising at least one electrically conductive layer structure (121-124, 131-133, 150; [0114], [0150], [0169], [0191]) and at least one electrically insulating layer structure (111, 112, 140, 160, 170; [0025], [0091], [0241], [0238]);
a main cavity (C1, [0306]) provided in the at least one electrically insulating layer structure (111, 112, 140, 160, 170; [0025], [0091], [0241], [0238]);
a first component (200, [0126]) placed in the main cavity (C1) ([0307]);
a first electrically insulating filling material (170, [0025], [0238]) filling or encapsulating the main cavity (C1) with the placed first component (200), embedding the first component (200) in the stack (layers 124 through 160);
a second component (420, [0316]) mounted on the first component (200) and in a cavity (labelled as C2 in Fig. 11w, [0311]) which is delimited by an interface surface of the stack (e.g., an interface of the insulating layer 160); and
a second electrically insulating filling (470, [0328]) which at least partially fills the cavity (C2) and extends up to the interface surface and thereby forms an interface (side surfaces of 470) with at least one of the at least one electrically insulating layer structure (160) (see Fig. 12, [0328]).
Regarding claim 5, Jo further teaches, in Fig. 12, a stop layer (312, [0246]) on an upper main surface of the first component (200) and configured for stopping a cavity formation process ([0246]).
Regarding claim 14, Jo further teaches that at least one of the first component and the second component is a thermally conductive block ([0220]-[0221], first component 200 has base layer 210 that may be silicon, which is thermally conductive).
Regarding claim 30, Jo teaches, in Figs. 11a-12, a method of manufacturing a component carrier ([0051]-[0052]), the method comprising:
providing a stack (layers 124 through 160) comprising at least one electrically conductive layer structure (121-124, 131-133, 150; [0114], [0150], [0169], [0191]) and at least one electrically insulating layer structure (111, 112, 140, 160; [0025], [0091], [0241]) (see Fig. 11r);
providing a main cavity (C1) in the at least one electrically insulating layer structure (111/112/140/160) (see Fig. 11s, [0306]);
placing a first component (200, [0126]) in the main cavity (C1) (see Fig. 11t, [0307]);
filling or encapsulating the main cavity (C1) with the placed first component (200) by a first electrically insulating filling material (170, [0025], [0238]) embedding the first component (200) in the stack (layers 124 through 160 and which now includes 170) (see Fig. 11u, [0308]);
mounting a second component (420, [0316]) on the first component (200) and in a cavity (labelled as C2 in Fig. 11w, [0311]) which is delimited by an interface surface of the stack (e.g., an interface of the insulating layer 160) (see Fig. 12, [0315]); and
at least partially filling the cavity (C2) with a second electrically insulating filling (470, [0328]) which extends up to the interface surface and thereby forms an interface (side surfaces of 470) with at least one of the at least one electrically insulating layer structure (160) (see Fig. 12, [0328]).
Regarding claim 31, Jo further teaches using alignment marks for embedding the first component (200) (see Fig. 11t, [0307], pads 121 act as alignment marks) and for mounting the second component (420) (see Fig. 12, [0315], pads 121 act as alignment marks).
Regarding claim 34, Jo further teaches, in Fig. 11v, that the cavity (C2) is formed by use of a stop layer (312, [0246]) or a releasable layer on an upper main surface of the first component (200), wherein the stop layer (312) is configured for enhancing a cavity formation process ([0246]).
Claims 1, 11, and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US 20230189444, hereinafter “Chen I”).
Regarding claim 1, Chen I teaches, in Fig. 2, a component carrier (100, [0066]) comprising:
a stack comprising at least one electrically conductive layer structure (1012, 2012, 2014; [0067], [0070]) and at least one electrically insulating layer structure (101, 201, 1015; [0067]-[0069]);
a main cavity (1013, [0067]) provided in the at least one electrically insulating layer structure (101/201/1015);
a first component (1041, [0067]) placed in the main cavity (1013);
a first electrically insulating filling material (1015, [0069], [0093]) filling or encapsulating the main cavity (1013) with the placed first component (1041), embedding the first component in the stack (1012, 2012, 2014, 101, 201, 1015);
a second component (1043, [0112]) mounted on the first component (1041) and in a cavity (2016, [0070]) which is delimited by an interface surface of the stack (e.g. interface of 201); and
a second electrically insulating filling (2018, [0070], [0113]) which at least partially fills the cavity (2016) and extends up to the interface surface and thereby forms an interface with at least one of the at least one electrically insulating layer structure (101, 201, 1015) (see Fig. 2).
Regarding claim 11, Chen I further teaches, in Fig. 2, that the first component (1041) and the second component (1043) are electrically coupled with each other indirectly via at least one of the at least one electrically conductive layer structure (1012, 2012, 2014).
Regarding claim 15, Chen I further teaches, in Fig. 2, that a center to center distance between adjacent pads (4012, [0072]) of the second component (1043) is smaller than a respective center to center distance between adjacent pads (3012, [0071]) of the first component (1041).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 20230071812) in view of Eid et al. (US 20190214328) and Trindade et al. (US 20230058681).
Regarding claim 2, Jang teaches the limitations of claim 1. Jang further teaches, in Fig. 6A, a third component (300, [0025]) mounted on the second component (200) and in a further cavity (the part of the cavity filled by 400 surrounding 300) which is delimited by a further interface surface of the stack (e.g. interface of 520), and
a further electrically insulating filling (the part of 400 surrounding 300) which at least partially fills the further cavity and extends up to the further interface surface and thereby forms an interface with at least one of the at least one electrically insulating layer structure (520).
Jang does not teach that an area defined by a bottom of the further cavity is greater than an area defined by the third component.
In a similar field of endeavor, Eid teaches that an area defined by a bottom of the further cavity (filled by 1114, [0061]) is greater than an area defined by the third component (1110, [0061]), so that heat can be conveyed from the area not covered by the third component ([0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the areas of the third component and cavity of Jang with the areas of Eid, so that heat can be conveyed from the area not covered by the third component ([0062]).
However, Jang in view of Eid does not explicitly teach that an area defined by a bottom of the further cavity is greater than an area defined by the third component of a percentage range from 1 to 20%. Nonetheless, the skilled artisan would know too that the areas would impact positioning accuracy (Trindade, [0054]; The last two sentences explain that the cavity should have an area that is slightly larger than the component, because for example, if the component is too small for the cavity, placing that component would be “too inaccurate”).
The specific claimed areas, absent any criticality, is only considered to be the “optimum” areas disclosed by Jang in view of Eid and Trindade that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired positioning accuracy, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as an area defined by a bottom of the further cavity being greater than an area defined by the third component of a percentage range from 1 to 20% is used, as already suggested by Jang in view of Eid and Trindade.
Since the applicant has not established the criticality (see next paragraph) of the areas stated, and since these areas are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Jang in view of Eid and Trindade.
Please note that the specification contains no disclosure of either the critical nature of the claimed areas or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20230189444, hereinafter “Chen I”) in view of Trindade et al. (US 20230058681).
Regarding claim 3, Chen I teaches the limitations of claim 1. Chen I further teaches, in Fig. 2, a third component (1042, [0069]) mounted side-by-side with the second component (1043) on the first component (1041), wherein for example the cavity (2016) extends along a (horizontal) direction from the second component (1043) to the third component (1042) with a width defined on the bottom of the cavity (2016) that is greater than the width of the respective second (1043) and third components (1042) (see Fig. 2).
However, Chen I does not explicitly teach that an area defined by a bottom of the further cavity is greater than an area defined by the third component of a percentage range from 1 to 20%. Nonetheless, the skilled artisan would know too that the areas would impact positioning accuracy (Trindade, [0054]; The last two sentences explain that the cavity should have an area that is slightly larger than the component, because for example, if the component is too small for the cavity, placing that component would be “too inaccurate”).
The specific claimed areas, absent any criticality, is only considered to be the “optimum” areas disclosed by Chen I in view of Trindade that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired positioning accuracy, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as an area defined by a bottom of the further cavity being greater than an area defined by the third component of a percentage range from 1 to 20% is used, as already suggested by Chen I in view of Trindade.
Since the applicant has not established the criticality (see next paragraph) of the areas stated, and since these areas are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Chen I in view of Trindade.
Please note that the specification contains no disclosure of either the critical nature of the claimed areas or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US 20250323135) in view of Chen (US 20180366393, hereinafter “Chen II”).
Regarding claim 32, Jo teaches the limitations of claim 30. Jo further teaches, in Fig. 14, that pads (610, [0353]) of the second component (420) or a third component (450, [0316]) are directly exposed at an external (top) main surface of the stack (layers 124 through 160).
Jo does not teach that the pads of the first component, the second component, or the third component are connected to a sputtered layer on the external main surface of the stack.
In a similar field of endeavor, Chen II teaches, in Fig. 2C, that the pads ([0016]) of the second component (7, [0015]) are connected to a sputtered layer (portion of 9 above substrate 1, [0012], [0016]) on the external main (top) surface of the stack (1 and portion of 5 within 1, [0010], [0012]),
in order to reduce the thickness of the packaging structure ([0012]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of manufacturing a component carrier of Jo with the connection of the pads to a sputtered layer of Chen II, in order to reduce the thickness of the packaging structure ([0012]).
Regarding claim 33, Jo in view of Chen II teaches the limitations of claim 32. Chen II further teaches that a top side of the stack (1/5) and the pads ([0016]) of the first component, the second component (7, [0015]) or the third component are ground ([0011]-[0012], [0015], Fig. 1D, second component 7 and its pads are made in the same manner as for first component 3);
thereafter, the electrically conductive structures (9, [0016]) are sputtered on a ground surface (top surface) of the stack (1/5) and the pads of the first component, the second component (7) or the third component ([0012], [0016]);
thereafter, the sputtered electrically conductive structures (9) are patterned ([0012], [0016]).
Conclusion
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
