Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 8/07/2026.
Claims 1-20 are currently pending.
Claims 1-20 have been examined.
Response to Arguments
The objection to the title is withdrawn in light of the amendment to the title.
Applicant’s arguments, see page 3, filed 8/7/2026, with respect to the rejection(s) of claims 1-3 under 35 U.S.C. 103 have been fully considered and are overall persuasive. In particular the examiner finds that the interpretation of Lim presented in the Office Action dated 5/15/2025 does not show that the thickness T2 is “half or less” than thickness T1. However, the examiner does find that Lim is not improper for being able to teach dimension or relative thickness. Lim at [0028] states that features such as the shape, size, and ratio are examples. These examples are intended to teach a person of ordinary skill in the art how to make the device and therefore, the figures can be used to show relative thickness and dimensions of the figure. However, since other arguments regarding the Lim and the specific teachings of certain dimensions were found to be persuasive and the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a new interpretation of Park and Lim.
Claim Interpretation
Regarding claims 1-3, the thickness of the region of the second portion of the EL layer being the shortest distance, which could be in the y/horizontal axis. This interpretation is supported by the applicants Fig. 14 and specification at [0181] – [0182].
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 6, 15, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. US 20210020725 A1 (hereinafter Park) in view of Lim et al. US 20210043705 A1 (hereinafter Lim).
The following annotated drawing from Lim will be used in discussion of the claims.
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Regarding claim 1, Park discloses:
A display apparatus (Park, Figs. 5-10, a display device 1 shown in different views) comprising:
a first wiring; (Park, Fig. 6, conductive layer 1300, which includes layers 1310, 1320, 1330, 1350, 1360, 1370, 1380 and 1390)
a second wiring; (Fig. 6, gate conductive layer 1200, includes 1210, 1220, 1250, and 1260)
a third wiring; (Fig 7, second conductive layer 1400, includes 1410, 1420, 1240, 1450, and 1460, 1470, and 1480)
a pixel electrode; (Fig. 6, pixel electrodes PXE including pixel electrode PXE1 and PXE3)
an EL layer; and (Fig. 6, light emitting layer EML and [0074] the light emitting layer EML is an organic light emitting layer.)
an insulating layer, (Fig. 8, [0073], pixel defining layer PDL is an insulating material.)
wherein the first wiring (conductive layer 1300) extends in a first direction (first direction DR1) and is supplied with a source signal, ([0124], conductive layer 1300 form a source electrode)
wherein the second wiring (gate conductive layer 1200) extends in a second direction (second direction DR2) intersecting with the first direction ([0106] DR1 and DR2 are intersecting) and is supplied with a gate signal, ([0005], gate signal provided to a gate line.)
wherein a constant potential is applied to the third wiring, ([0157], The common electrode CME applies has a potential to the third wiring 1470.)
wherein the first wiring (conductive layer 1300) and the pixel electrode (pixel electrodes PXE) are provided to overlap with each other with the third wiring therebetween, (See Fig. 8, conductive layer 1350 and pixel electrodes PEX3 overlap and conductive layer 1450 is between the two.)
wherein the insulating layer (pixel defining layer PDL) comprises a portion in contact with part of a top surface of the pixel electrode (pixel electrode PXE) and a portion in contact with a side surface of the pixel electrode, (See Fig. 8)
wherein the EL layer (light emitting layer EML) comprises a first portion in contact with another part of the top surface of the pixel electrode (pixel electrode PXE) and a second portion positioned over the insulating layer (pixel defining layer PDL), (See Fig. 8) and
Park does not appear to disclose “wherein the second portion comprises a region whose thickness is half or less of thickness of the first portion.”
Lim, which teaches a display device using an organic light emitting display manufacture in such a way as to prevent leakage current between adjacent pixels (Lim, Summary, [0006]), discloses:
wherein the EL layer (Fig. 4 and 6, light emitting layer 131) comprises a first portion (See annotated Fig.6 , first portion P1) in contact with another part of the top surface of the pixel electrode (first electrode 121) and a second portion (annotated Fig. 6, second portion P2) positioned over the insulating layer (bank 125), and
wherein the second portion (annotated Fig. 6, second portion P2) comprises a region (Region as defined by the portion of the light emitting layer 131 that is within R2) whose thickness is half or less of thickness of the first portion. (annotated Fig. 6, Thickness T1 of P1 is more than thickness T2 of R2 within P2.)
However, the ordinary artisan would have recognized the claimed thickness range to be a result effective variable. In this case controlling the thickness of the EL layer in both Lim and specification result in controlling the leakage current. (Lim, [0066] and [0075-0076]) Thus, it would have been obvious to prevent leakage current by controlling the thickness of the EL layers in the trench T the device of within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park to have the second portion comprises a region whose thickness is half or less of thickness of the first portion as taught by Lim for purposes of having thinner layer of the light emitting stack near the edges to reduce and prevent leakage current between adjacent subpixels (Lim, [0066] and [0075-0076]). This would increase the display resolution.
Regarding claim 8, Park and Lim disclose all the elements of claim 1.
Park further discloses:
wherein the third wiring (Fig. 7, second conductive layer 1400) has a grid-like top surface shape, (Fig. 1, shows that the display area DPA has pixels PX in an array and Fig. 7 shows that the top surface would be in a grid-like shape to fit within the array.) and the third wiring comprises a third portion extending in the first direction and a fourth portion extending in the second direction, and (There is a portion of the second conductive layer 1400 that direction DR1 and a portion in direction DR2.)
wherein the pixel electrode (pixel electrode PXE) and the first wiring (conductive layer 1300) are provided to overlap with each other with the third portion (conductive layer 1400) therebetween. (See Fig. 8, conductive layer 1350 and pixel electrodes PEX3 overlap and conductive layer 1450 is between the two.)
Regarding claim 13, Park and Lim disclose all the elements of claim 1.
Park further discloses:
a connector or an integrated circuit. (Park, [0065], the display device 1 has external devices with connectors.)
Regarding claim 14, Park and Lim disclose all the elements of claim 13.
Park further discloses:
at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button. (Park, [0003], the display can be used with a digital camera.)
Regarding claim 2, Park discloses:
A display apparatus (Park, Figs. 4-10, a display device 1 shown in different views) comprising:
a first wiring; (Park, Fig. 6, conductive layer 1300, which includes layers 1310, 1320, 1330, 1350, 1360, 1370, 1380 and 1390)
a second wiring; (Fig. 6, gate conductive layer 1200, includes 1210, 1220, 1250, and 1260)
a third wiring; (Fig 7, second conductive layer 1400, includes 1410, 1420, 1240, 1450, and 1460, 1470, and 1480)
a pixel electrode; (Fig. 6, pixel electrodes PXE including pixel electrode PXE1 and PXE3)
a first transistor; (Fig. 4, the display device 1 includes at least transistor switching transistor SST which is in the third semiconductor layer 1130.)
a second transistor; (Fig. 4, the display device 1 includes at least transistor DRT, which is in semiconductor layer 1110)
an EL layer; and (Fig. 6, light emitting layer EML and [0074] the light emitting layer EML is an organic light emitting layer.)
an insulating layer, (Fig. 8, [0073], pixel defining layer PDL is an insulating material.)
wherein the first wiring (conductive layer 1300) extends in a first direction (first direction DR1) and is supplied with a source signal, ([0124], conductive layer 1300 form a source electrode)
wherein the second wiring (gate conductive layer 1200) extends in a second direction (second direction DR2) intersecting with the first direction ([0106] DR1 and DR2 are intersecting) and is supplied with a gate signal, ([0005], gate signal provided to a gate line.)
wherein a first potential is applied to the third wiring, ([0157], The common electrode CME applies has a first potential to the third wiring 1470.)
wherein the first wiring (conductive layer 1300) and the pixel electrode (pixel electrodes PXE) are provided to overlap with each other with the third wiring therebetween, (See Fig. 8, conductive layer 1350 and pixel electrodes PEX3 overlap and conductive layer 1450 is between the two.)
wherein one of a source and a drain of the first transistor (transistor SST) is electrically connected to the first wiring, (Fig. 4 and [0131], 1130 is the source electrode of the SST) and a gate of the first transistor is electrically connected to the second wiring, ([0135] gate of transistor SST is connected to gate conductive layer 1220.)
wherein one of a source and a drain of the second transistor is electrically connected to the pixel electrode, (Fig. 8, source and drain of transistor DRT is electrically connected to the pixel electrode PXE) and the other of the source and the drain of the second transistor is electrically connected to the third wiring, (Fig. 8, the other source drain electrically connected to conductive layer 1480.)
wherein the first transistor (Fig. first semiconductor layer 1110 and driving transistor DRT) and in which current flows in … [a] direction.
wherein the insulating layer (pixel defining layer PDL) comprises a portion in contact with part of a top surface of the pixel electrode (pixel electrode PXE) and a portion in contact with a side surface of the pixel electrode, (See Fig. 8)
wherein the EL layer (light emitting layer EML) comprises a first portion in contact with another part of the top surface of the pixel electrode (pixel electrode PXE) and a second portion positioned over the insulating layer (pixel defining layer PDL), (See Fig. 8) and…
Park does not appear to specifically disclose “the second transistor each comprise a semiconductor layer in which current flows in the first direction.” However, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions does not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)). In this case, nothing on the record indicates that the claimed the extension direction of the semiconductor layer in which the current flows would cause the structure to operate differently. This is a design matter that could be selected as appropriate by a person of ordinary skill in the art.
Park does not appear to disclose “wherein the second portion comprises a region whose thickness is half or less of thickness of the first portion.”
Lim, which teaches a display device using an organic light emitting display manufacture in such a way as to prevent leakage current between adjacent pixels (Lim, Summary, [0006]), discloses:
wherein the EL layer (Fig. 4 and 6, light emitting layer 131) comprises a first portion (See annotated Fig.6 , first portion P1) in contact with another part of the top surface of the pixel electrode (first electrode 121) and a second portion (annotated Fig. 6, second portion P2) positioned over the insulating layer (bank 125), and
wherein the second portion (annotated Fig. 6, second portion P2) comprises a region (Region as defined by the portion of the light emitting layer 131 that is within R2) whose thickness is half or less of thickness of the first portion. (annotated Fig. 6, Thickness T1 of P1 is more than thickness T2 of R2 within P2.)
However, the ordinary artisan would have recognized the claimed thickness range to be a result effective variable. In this case controlling the thickness of the EL layer in both Lim and specification result in controlling the leakage current. (Lim, [0066] and [0075-0076]) Thus, it would have been obvious to prevent leakage current by controlling the thickness of the EL layers in the trench T the device of within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park to have the second portion comprises a region whose thickness is half or less of thickness of the first portion as taught by Lim for purposes of having thinner layer of the light emitting stack near the edges to reduce and prevent leakage current between adjacent subpixels (Lim, [0066] and [0075-0076]). This would increase the display resolution.
Regarding claim 6, Park and Lim discloses all the elements of claim 2.
Park further discloses:
wherein one of a source and a drain of the third transistor is electrically connected to the fourth wiring, and the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth wiring, and the other of the source and the drain of the fourth transistor is electrically connected to the pixel electrode, and
wherein a second potential lower than the first potential is applied to the fourth wiring.
Park discloses that the number of transistors and capacitors included in each pixel driving circuit may be changed variously such as a 7 transistor substructure or 6 transistor structure. (Park, [0108]). In this case, nothing on the record indicates that claimed elements above perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)).
Regarding claim 17, Park and Lim disclose all the elements of claim 2.
Park further discloses:
wherein the third wiring (Fig. 7, second conductive layer 1400) has a grid-like top surface shape, (Fig. 1, shows that the display area DPA has pixels PX in an array and Fig. 7 shows that the top surface would be in a grid-like shape to fit within the array.) and the third wiring comprises a third portion extending in the first direction and a fourth portion extending in the second direction, and (There is a portion of the second conductive layer 1400 that direction DR1 and a portion in direction DR2.)
wherein the pixel electrode (pixel electrode PXE) and the first wiring (conductive layer 1300) are provided to overlap with each other with the third portion (conductive layer 1400) therebetween. (See Fig. 8, conductive layer 1350 and pixel electrodes PEX3 overlap and conductive layer 1450 is between the two.)
Regarding claim 3, Park discloses:
A display apparatus (Park, Figs. 5-10, a display device 1 shown in different views) comprising:
a first wiring; (Park, Fig. 6, conductive layer 1300, which includes layers 1310, 1320, 1330, 1350, 1360, 1370, 1380 and 1390)
a second wiring; (Fig. 6, gate conductive layer 1200, includes 1210, 1220, 1250, and 1260)
a third wiring; (Fig 7, second conductive layer 1400, includes 1410, 1420, 1240, 1450, and 1460, 1470, and 1480)
a pixel electrode; (Fig. 6, pixel electrodes PXE including pixel electrode PXE1 and PXE3)
a first transistor; (Fig. 4, the display device 1 includes at least transistor switching transistor SST which is in the third semiconductor layer 1130.)
a second transistor; (Fig. 4, the display device 1 includes at least transistor DRT, which is in semiconductor layer 1110)
an EL layer; and (Fig. 6, light emitting layer EML and [0074] the light emitting layer EML is an organic light emitting layer.)
an insulating layer, (Fig. 8, [0073], pixel defining layer PDL is an insulating material.)
wherein the first wiring (conductive layer 1300) extends in a first direction (first direction DR1) and is supplied with a source signal, ([0124], conductive layer 1300 form a source electrode)
wherein the second wiring (gate conductive layer 1200) extends in a second direction (second direction DR2) intersecting with the first direction ([0106] DR1 and DR2 are intersecting) and is supplied with a gate signal, ([0005], gate signal provided to a gate line.)
wherein a first potential is applied to the third wiring, ([0157], The common electrode CME applies has a first potential to the third wiring 1470.)
wherein the first wiring (conductive layer 1300) and the pixel electrode (pixel electrodes PXE) are provided to overlap with each other with the third wiring therebetween, (See Fig. 8, conductive layer 1350 and pixel electrodes PEX3 overlap and conductive layer 1450 is between the two.)
wherein one of a source and a drain of the first transistor (transistor SST) is electrically connected to the first wiring, (Fig. 4 and [0131], 1130 is the source electrode of the SST) and a gate of the first transistor is electrically connected to the second wiring, ([0135] gate of transistor SST is connected to gate conductive layer 1220.)
wherein one of a source and a drain of the second transistor is electrically connected to the pixel electrode, (Fig. 8, source and drain of transistor DRT is electrically connected to the pixel electrode PXE) and the other of the source and the drain of the second transistor is electrically connected to the third wiring, (Fig. 8, the other source drain electrically connected to conductive layer 1480.)
wherein the first transistor (Fig. first semiconductor layer 1110 and driving transistor DRT) and in which current flows in … [a] direction.
wherein the insulating layer (pixel defining layer PDL) comprises a portion in contact with part of a top surface of the pixel electrode (pixel electrode PXE) and a portion in contact with a side surface of the pixel electrode, (See Fig. 8)
wherein the EL layer (light emitting layer EML) comprises a first portion in contact with another part of the top surface of the pixel electrode (pixel electrode PXE) and a second portion positioned over the insulating layer (pixel defining layer PDL), (See Fig. 8) and…
Park does not appear to specifically disclose “the second transistor each comprise a semiconductor layer in which current flows in the second direction.” However, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions does not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)). In this case, nothing on the record indicates that the claimed the extension direction of the semiconductor layer in which the current flows would cause the structure to operate differently. This is a design matter that could be selected, as appropriate by a person of ordinary skill in the art.
Park does not appear to disclose “wherein the second portion comprises a region whose thickness is half or less of thickness of the first portion.”
Lim, which teaches a display device using an organic light emitting display manufacture in such a way as to prevent leakage current between adjacent pixels (Lim, Summary, [0006]), discloses:
wherein the EL layer (Fig. 4 and 6, light emitting layer 131) comprises a first portion (See annotated Fig.6 , first portion P1) in contact with another part of the top surface of the pixel electrode (first electrode 121) and a second portion (annotated Fig. 6, second portion P2) positioned over the insulating layer (bank 125), and
wherein the second portion (annotated Fig. 6, second portion P2) comprises a region (Region as defined by the portion of the light emitting layer 131 that is within R2) whose thickness is half or less of thickness of the first portion. (annotated Fig. 6, Thickness T1 of P1 is more than thickness T2 of R2 within P2.)
However, the ordinary artisan would have recognized the claimed thickness range to be a result effective variable. In this case controlling the thickness of the EL layer in both Lim and specification result in controlling the leakage current. (Lim, [0066] and [0075-0076]) Thus, it would have been obvious to prevent leakage current by controlling the thickness of the EL layers in the trench T the device of within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park to have the second portion comprises a region whose thickness is half or less of thickness of the first portion as taught by Lim for purposes of having thinner layer of the light emitting stack near the edges to reduce and prevent leakage current between adjacent subpixels (Lim, [0066] and [0075-0076]). This would increase the display resolution.
Regarding claim 15, Park and Lim discloses all the elements of claim 3.
Park further discloses:
wherein one of a source and a drain of the third transistor is electrically connected to the fourth wiring, and the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth wiring, and the other of the source and the drain of the fourth transistor is electrically connected to the pixel electrode, and
wherein a second potential lower than the first potential is applied to the fourth wiring.
Park discloses that the number of transistors and capacitors included in each pixel driving circuit may be changed variously such as a 7 transistor substructure or 6 transistor structure. (Park, [0108]). In this case, nothing on the record indicates that claimed elements above perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)).
Regarding claim 18, Park and Lim disclose all the elements of claim 3.
Park further discloses:
wherein the third wiring (Fig. 7, second conductive layer 1400) has a grid-like top surface shape, (Fig. 1, shows that the display area DPA has pixels PX in an array and Fig. 7 shows that the top surface would be in a grid-like shape to fit within the array.) and the third wiring comprises a third portion extending in the first direction and a fourth portion extending in the second direction, and (There is a portion of the second conductive layer 1400 that direction DR1 and a portion in direction DR2.)
wherein the pixel electrode (pixel electrode PXE) and the first wiring (conductive layer 1300) are provided to overlap with each other with the third portion (conductive layer 1400) therebetween. (See Fig. 8, conductive layer 1350 and pixel electrodes PEX3 overlap and conductive layer 1450 is between the two.)
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Lim as applied to claims 1, 2, and 3 above, and further in view of Koyama et al. US 20060202206 A1 (hereinafter Koyama).
Regarding claim 4, Park and Lim disclose all the elements claim 2 above.
Park and Lim do not appear to disclose:
“further comprising a plurality of dummy layers,
wherein the dummy layer comprises the same semiconductor material as the semiconductor layer,
wherein the dummy layer comprises a portion having substantially the same top surface shape as the semiconductor layer, and
wherein the plurality of dummy layers and the semiconductor layer are placed at a regular interval in the second direction.”
Koyama, which teaches a semiconductor device with a dummy pattern or dummy transistor (Koyama, [0118]), discloses:
further comprising a plurality of dummy layers, (Fig. 11A-E, the dummy transistor has dummy layers as part of the transistor.)
wherein the dummy layer comprises the same semiconductor material as the semiconductor layer, ([0119], The dummy transistors 252 a and 252 b can be provided in the same manner as the transistor 251.)
wherein the dummy layer comprises a portion having substantially the same top surface shape as the semiconductor layer, and (Fig. 11C, shows the dummy transistor having substantially the same top surface shape as the semiconductor layer.)
wherein the plurality of dummy layers and the semiconductor layer are placed at a regular interval in the second direction. ( Fig. 11D, dummy transistors 254 a to 254 h may be provided on all sides of the transistor 251, therefore the dummy layers are placed at regular intervals in a second direction being the y-direction.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park and Lim to have further comprising a plurality of dummy layers, wherein the dummy layer comprises the same semiconductor material as the semiconductor layer, wherein the dummy layer comprises a portion having substantially the same top surface shape as the semiconductor layer, and wherein the plurality of dummy layers and the semiconductor layer are placed at a regular interval in the second direction as taught by Koyama for purposes of preventing damage or destruction of the transistor due to static electricity or stress. (Koyama, [0118].)
Regarding claim 5, Park and Lim disclose all the elements of claim 3 above.
Park and Lim do not appear to disclose:
“further comprising a plurality of dummy layers,
wherein the dummy layer comprises the same semiconductor material as the semiconductor layer,
wherein the dummy layer comprises a portion having substantially the same top surface shape as the semiconductor layer, and
wherein the plurality of dummy layers and the semiconductor layer are placed at a regular interval in the first direction.”
Koyama, which teaches a semiconductor device with a dummy pattern or dummy transistor (Koyama, [0118]), discloses:
further comprising a plurality of dummy layers, (Fig. 11A-E, the dummy transistor has dummy layers as part of the transistor.)
wherein the dummy layer comprises the same semiconductor material as the semiconductor layer, ([0119], The dummy transistors 252 a and 252 b can be provided in the same manner as the transistor 251.)
wherein the dummy layer comprises a portion having substantially the same top surface shape as the semiconductor layer, and (Fig. 11C, shows the dummy transistor having substantially the same top surface shape as the semiconductor layer.)
wherein the plurality of dummy layers and the semiconductor layer are placed at a regular interval in the first direction. ( Fig. 11D, dummy transistors 254 a to 254 h may be provided on all sides of the transistor 251, therefore the dummy layers are placed at regular intervals in a first direction being the x-direction.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park and Lim to have further comprising a plurality of dummy layers, wherein the dummy layer comprises the same semiconductor material as the semiconductor layer, wherein the dummy layer comprises a portion having substantially the same top surface shape as the semiconductor layer, and wherein the plurality of dummy layers and the semiconductor layer are placed at a regular interval in the first direction as taught by Koyama for purposes of preventing damage or destruction of the transistor due to static electricity or stress. (Koyama, [0118].)
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Lim as applied to claims 1, 2, and 3 above, and further in view of Yoshinobu US 20180019343 A1 (hereinafter Yoshinobu).
Regarding claim 7, Park and Lim disclose all the elements claim 2 above.
Park further discloses a fifth transistor because Park discloses that the number of transistors and capacitors included in each pixel driving circuit may be changed variously such as a 7 transistor substructure or 6 transistor structure. (Park, [0108]). In this case, nothing on the record indicates that claimed elements above perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)).
Park also further discloses wherein the fifth transistor is a transistor whose channel is formed in silicon. (Park, [0101], display device 1, includes between first substate 10 and a second substrate 20 a filing layer 30 which include Si-based organic material. Therefore, any transistor formed would by necessity be formed in silicon.)
Park also discloses: wherein the semiconductor layer comprises one or both of indium and zinc. ([0132], semiconductor layer 1110 includes indium-gallium-zinc oxide (IGZO).)
Park does not appear to discloses:
wherein the first transistor and the second transistor are provided above the fifth transistor.
Yoshinobu, which teaches silicon-based transistor (Yoshinobu, Background [0003]), discloses
wherein the fifth transistor (transistor 351) is a transistor whose channel is formed in silicon, (Yoshinobu, Fig. 34B, transistor 351 is in a silicon substrate 300.)
wherein the first transistor (Fig. 34B, transistor 353) and the second transistor (transistor 352) are provided above the fifth transistor. (transistor 351)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park and Lim to have the first transistor and the second transistor are provided above the fifth transistor as taught by Yoshinobu for purposes of stacking two types of transistor reduces the surface area of the circuit therefore the plurality of circuits can be arranged with higher density. (Yoshinobu, [0383])
Regarding claim 16, Park and Lim disclose all the elements of claim 3 above.
Park further discloses a fifth transistor because Park discloses that the number of transistors and capacitors included in each pixel driving circuit may be changed variously such as a 7 transistor substructure or 6 transistor structure. (Park, [0108]). In this case, nothing on the record indicates that claimed elements above perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)).
Park also further discloses wherein the fifth transistor is a transistor whose channel is formed in silicon. (Park, [0101], display device 1, includes between first substate 10 and a second substrate 20 a filing layer 30 which include Si-based organic material. Therefore, any transistor formed would by necessity be formed in silicon.)
Park also discloses: wherein the semiconductor layer comprises one or both of indium and zinc. ([0132], semiconductor layer 1110 includes indium-gallium-zinc oxide (IGZO).)
Park does not appear to discloses:
wherein the first transistor and the second transistor are provided above the fifth transistor.
Yoshinobu, which teaches silicon-based transistor (Yoshinobu, Background [0003]), discloses
wherein the fifth transistor (transistor 351) is a transistor whose channel is formed in silicon, (Yoshinobu, Fig. 34B, transistor 351 is in a silicon substrate 300.)
wherein the first transistor (Fig. 34B, transistor 353) and the second transistor (transistor 352) are provided above the fifth transistor. (transistor 351)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park and Lim to have the first transistor and the second transistor are provided above the fifth transistor as taught by Yoshinobu for purposes of stacking two types of transistor reduces the surface area of the circuit therefore the plurality of circuits can be arranged with higher density. (Yoshinobu, [0383])
Claims claim 9-12, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Lim as applied to claims 1, 2, and 3 above, and further in view of Shao et al. US 20200212124 A1 (hereinafter Shao).
Regarding claim 9, Park and Lim disclose all the elements claim 1 above.
Park further teaches:
comprising a plurality of pixel electrodes, (Fig. 1, a plurality of pixel electrodes PXE in the array with the display device 1.)
wherein a light-emitting region is provided over each of the pixel electrodes (Fig. 6, light emitting layer EML is over pixel electrodes PXE ), and
Park does not appear to teach:
wherein the plurality of light-emitting regions are arranged so that one of the light- emitting regions is surrounded by six of the light-emitting regions in a plan view.
Shao, which teaches, a OLED having a pixel regions that is designed by six boundary lines (Shao, Abstract), discloses:
wherein the plurality of light-emitting regions (FIGS. 2-5, arrangement of a plurality of aperture regions o fa display panel.) are arranged so that one of the light-emitting regions is surrounded by six of the light-emitting regions in a plan view. (Fig. 2, the aperture region of the light emitting regions has a hexagon shape.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park and Lim to have the plurality of light-emitting regions are arranged so that one of the light- emitting regions is surrounded by six of the light-emitting regions in a plan view as taught by Shao for purposes of improve the resolution of the OLED. (Shao, [0030].)
Regarding claim 10, Park, Lim, and Shao disclose all the elements claim 9 above.
Shao further discloses:
wherein the light-emitting region has a substantially hexagonal top surface shape, and wherein the light-emitting region has a substantially hexagonal top surface shape, and (Fig. 2, the aperture region of the light emitting regions has a hexagon shape.)
wherein the light-emitting region has a top surface shape in which interior angles of two opposite corners of six corners are each greater than 120o (Fig. 4., The apex angle a2 of the hexagon is equal to 143.13°.),and interior angles of the other four of the six corners are each less than 120°. (Fig. 4., The apex angle a1 of the hexagon is equal to 108.44°.)
Regarding claim 11, Park, Lim, and Shao disclose all the elements claim 9 above.
Shao further discloses:
wherein the light-emitting region has a substantially hexagonal top surface shape, and wherein the light-emitting region has a substantially hexagonal top surface shape, and (Fig. 2, the aperture region of the light emitting regions has a hexagon shape.)
wherein the light-emitting region has a top surface shape in which interior angles of two opposite corners of six corners are each greater than 120o (Fig. 4., The apex angle a2 of the hexagon is equal to 143.13°.),and interior angles of the other four of the six corners are each less than 120°, (Fig. 4., The apex angle a1 of the hexagon is equal to 108.44.), and lengths of the other four sides are equal to one another. (Fig.4, having four long sides 12.)
Regarding claim 12, Park, Lim, and Shao disclose all the elements claim 9 above.
Shao further discloses:
wherein three adjacent light-emitting regions of the light-emitting regions are positioned to be on vertices of an isosceles triangle. (Fig. 3, [0028], The pixel unit 3 for display in a shape of an isosceles right triangle is 3a in the row direction.)
Regarding claim 19, Park and Lim disclose all the elements claim 2 above.
Park further teaches:
comprising a plurality of pixel electrodes, (Fig. 1, a plurality of pixel electrodes PXE in the array with the display device 1.)
wherein a light-emitting region is provided over each of the pixel electrodes (Fig. 6, light emitting layer EML is over pixel electrodes PXE ), and
Park does not appear to teach:
wherein the plurality of light-emitting regions are arranged so that one of the light- emitting regions is surrounded by six of the light-emitting regions in a plan view.
Shao, which teaches, a OLED having a pixel regions that is designed by six boundary lines (Shao, Abstract), discloses:
wherein the plurality of light-emitting regions (FIGS. 2-5, arrangement of a plurality of aperture regions o fa display panel.) are arranged so that one of the light-emitting regions is surrounded by six of the light-emitting regions in a plan view. (Fig. 2, the aperture region of the light emitting regions has a hexagon shape.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park and Lim to have the plurality of light-emitting regions are arranged so that one of the light- emitting regions is surrounded by six of the light-emitting regions in a plan view as taught by Shao for purposes of improve the resolution of the OLED. (Shao, [0030].)
Regarding claim 20, Park and Lim disclose all the elements of claim 3 above.
Park further teaches:
comprising a plurality of pixel electrodes, (Fig. 1, a plurality of pixel electrodes PXE in the array with the display device 1.)
wherein a light-emitting region is provided over each of the pixel electrodes (Fig. 6, light emitting layer EML is over pixel electrodes PXE ), and
Park does not appear to teach:
wherein the plurality of light-emitting regions are arranged so that one of the light- emitting regions is surrounded by six of the light-emitting regions in a plan view.
Shao, which teaches, a OLED having a pixel regions that is designed by six boundary lines (Shao, Abstract), discloses:
wherein the plurality of light-emitting regions (FIGS. 2-5, arrangement of a plurality of aperture regions o fa display panel.) are arranged so that one of the light-emitting regions is surrounded by six of the light-emitting regions in a plan view. (Fig. 2, the aperture region of the light emitting regions has a hexagon shape.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park and Lim to have the plurality of light-emitting regions are arranged so that one of the light- emitting regions is surrounded by six of the light-emitting regions in a plan view as taught by Shao for purposes of improve the resolution of the OLED. (Shao, [0030].)
Conclusion
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/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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