DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 26, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 8 are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by Chamberlin et al. (US 20080142249 A1)
Regarding Claim 1 – Chamberlin teaches a component carrier comprising (Fig 5; 500): a stack comprising at least one electrically insulating layer structure (Fig 5; 502; Chamberlin [0024]) and at least one electrically conductive layer structure (Fig 5; 504; Chamberlin [0024]); a first metal trace comprising a rough surface (Fig 4; 424b; Fig 5; 508; Chamberlin [0023, 0025]); and a second metal trace arranged adjacent to the first metal trace, comprising a smooth surface (Fig 4; 424a; Fig 5; 506/508; Chamberlin [0023-0025]); wherein the component carrier is configured to guide at least one of high-frequency, HF, signals and high-speed signals through the second metal trace (Fig 5; 506; Chamberlin [0025]; see also Chamberlin [0020]).
Regarding Claim 3 – Chamberlin teaches the component carrier according to claim 1, wherein the second metal trace comprises rough surface portions and smooth surface portions in an alternating manner (Chamberlin [0027] states “A first region 606 and a third region 610… are smooth while a second region 608… is rough”).
Regarding Claim 8 – Chamberlin teaches the component carrier according to claim 1, further comprising: a resin layer structure arranged on top of the first metal trace (Chamberlin [0029]), and/or a non-resin layer structure arranged on top of the second metal trace.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chamberlin et al. (US 20080142249 A1) and in further view of Harkness et al. (US 20160174364 A1)
Regarding Claim 2 – Chamberlin teaches the component carrier according to claim 1, but does not explicitly disclose wherein the rough surface comprises a surface roughness of more than 500 nm; and/or wherein the smooth surface comprises a surface roughness of less than 500 nm.
Harkness teaches the rough surface comprises a surface roughness of more than 500 nm (Figs 4A; 402 and Fig 4C; 410; Harkness [0055] states “approximately 2 microns” i.e., > 500 nm); and/or wherein the smooth surface comprises a surface roughness of less than 500 nm (Figs 4B; 404 and Fig 4D; 412; Harkness [0058] states “approximately 0.4 micron” i.e., 400 nm < 500 nm).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Chamberlin with the rough surface comprises a surface roughness of more than 500 nm; and/or wherein the smooth surface comprises a surface roughness of less than 500 nm as taught by Harkness because Harkness [0054] states “roughened regions… can provide adequate adhesion for joining multiple layers of a multilayer PCB, and preventing delamination of the PCB. The smoothed regions can reduce signal loss for signals traversing the circuit traces”.
Regarding Claim 5 – Chamberlin teaches the component carrier according to claim 1, but does not explicitly disclose wherein the first metal trace and the second metal trace are embedded in a common encapsulation material.
Harkness teaches the first metal trace and the second metal trace are embedded in a common encapsulation material (Harkness claim 62 states “insulating matrix” i.e., the common encapsulating dielectric; “signal traces” embedded therein).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Chamberlin with the first metal trace and the second metal trace are embedded in a common encapsulation material as taught by Harkness because embedding the traces within a common dielectric material in a multilayer stack is a common practice while preserving smooth routing surfaces for signal loss reduction.
Regarding Claim 6 – Chamberlin teaches the component carrier according to claim 1, but does not explicitly disclose wherein only the second metal trace is at least partially covered by a protection layer.
Harkness teaches only the second metal trace is at least partially covered by a protection layer (Figs 5D-5E; 540; Harkness [0065-0066]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Chamberlin with only the second metal trace is at least partially covered by a protection layer as taught by Harkness because Harkness [0066] uses the protection to preserve signal carrying region “cover a majority of a region… that carries a transmitted signal”.
Claims 4, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chamberlin et al. (US 20080142249 A1) and in further view of Day et al. (US 20040007313 A1)
Regarding Claim 4 – Chamberlin teaches the component carrier according to claim 1, but does not explicitly disclose wherein the HF signals comprise a frequency of at least 1 GHz.
Day teaches the HF signals comprise a frequency of at least 1 GHz (Day [0005] states “High frequency applications… i.e. one GHz and above”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Chamberlin with the HF signals comprise a frequency of at least 1 GHz as taught by Day because the smooth surface reduces losses at those frequencies “one GHz and above”.
Regarding Claim 7 – Chamberlin teaches the component carrier according to claim 1, but does not explicitly disclose further comprising: a cavity in the stack, wherein the bottom and/or the sidewalls of the cavity are at least partially covered by the second metal trace.
Day teaches a cavity in the stack (Figs 1-3; 17/28/29/32; Day [0018]), wherein the bottom and/or the sidewalls of the cavity are at least partially covered (Figs 1-3; plated through hole 33; Day [0018]) by the second metal trace (Figs 1-3; land 16 contacting copper 33; Day [0018]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Chamberlin with a cavity in the stack, wherein the bottom and/or the sidewalls of the cavity are at least partially covered by the second metal trace as taught by Day because Day [0016] states “the signal lines are left smooth to promote the most advantageous propagation of signals therealong”.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chamberlin et al. (US 20080142249 A1) and in further view of Brist et al. (US 20070154155 A1)
Regarding Claim 9 – Chamberlin teaches the component carrier according to claim 1, but does not explicitly disclose comprising at least one of the following features: further comprising: an adhesion promotor arranged between the non-resin layer structure and the second metal trace, wherein the adhesion promoter comprises polyimide, PI; a further second metal trace arranged on top of the non-resin layer structure and/or on top of the cavity, such that the non-resin layer structure or the cavity functions as a waveguide.
Brist teaches a further second metal trace arranged on top of the non-resin layer structure and/or on top of the cavity (Fig 3; 342; Brist [0054]), such that the non-resin layer structure or the cavity functions as a waveguide (Brist [0022] states “a channel is formed in printed circuit board material… to form… an embedded waveguide” and [0045] states “a channel, trench, and/or cavity are formed”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Chamberlin with a further second metal trace arranged on top of the non-resin layer structure and/or on top of the cavity, such that the non-resin layer structure or the cavity functions as a waveguide as taught by Brist because Brist [0006] states “In order to ensure a minimal loss and to guide the energy of such high frequencies, one solution might be to use waveguide structures”.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chamberlin et al. (US 20080142249 A1) and in further view of Carlson et al. (US 20170079131 A1)
Regarding Claim 11 – Chamberlin teaches the component carrier according to claim 1, but does not explicitly disclose comprising at least one of the following features: wherein the second metal trace comprises the smooth surface at the top portion, while at least one sidewall portion comprises a rough surface; and/or wherein the second metal trace comprises the smooth surface at at least one sidewall, while the top portion comprise a rough surface; wherein the component carrier comprises a peripheral portion and a central portion, and wherein the surface roughness of first metal traces at the peripheral portion of the component carrier is larger than the surface roughness of first metal traces at the central portion of the component carrier; wherein at least one first metal trace is larger than the adjacent second metal trace, wherein said at least one first metal trace is configured as a non-functional electrically conductive.
Carlson teaches at least one first metal trace is larger than the adjacent second metal trace, wherein said at least one first metal trace is configured as a non-functional electrically conductive (Fig 5B shows plane 186 as the large adjacent conductive region relative to the narrow trace 184; Carlson [0032]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Chamberlin with at least one first metal trace is larger than the adjacent second metal trace, wherein said at least one first metal trace is configured as a non-functional electrically conductive as taught by Carlson because Carlson (Abstract) states “The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus”.
Conclusion
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/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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