DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 29, 2026, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed June 26, 2026 have been fully considered. To the extent the arguments are directed to Chamberlin alone, they are moot in view of the new grounds of rejection set forth below. The remaining arguments are not persuasive for the reasons set forth in the rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 4, 6, 8, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chamberlin et al. (US 20080142249 A1) and in further view of Day et al. (US 20040007313 A1)
Regarding Claim 1 – Chamberlin teaches a component carrier comprising (Fig 5; 500): a stack comprising at least one electrically insulating layer structure (Fig 5; 502; Chamberlin [0024]) and at least one electrically conductive layer structure (Fig 5; 504; Chamberlin [0024]); a first metal trace comprising a rough surface (Fig 4; 424b; Fig 5; 508; Chamberlin [0023, 0025]); and a second metal trace arranged adjacent to the first metal trace, comprising a smooth surface (Fig 4; 424a; Fig 5; 506/508; Chamberlin [0023-0025]); wherein the component carrier is configured to guide at least one of high-frequency signals and high-speed signals through the second metal trace (Fig 5; 506; Chamberlin [0025]; see also Chamberlin [0020]).
Chamberlin does not explicitly disclose wherein the second metal trace is at least partially covered by a protection layer.
Day teaches the second metal trace is at least partially covered by a protection layer (Figs 5 and 8; signal line or voltage plane, permanent resin mask; Day [0029] states “a permanent mask” comprising resin screen printed onto a signal plane and “covering only those areas that are to remain smooth”). Day further teaches curing the permanent mask, roughening the exposed areas, and laminating the layers to form the resulting composite board structure.
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Chamberlin with the second metal trace is at least partially covered by a protection layer as taught by Day because Chamberlin [0021] teaches “sufficient adhesion… without compromising electrical performance” while Day [0029] teaches “a permanent mask” “covering only those areas that are to remain smooth”, so that the portions used for high speed signaling remain smooth while other exposed portions are roughened to improve adhesion.
Regarding Claim 2 – Chamberlin in view of Day teaches the component carrier according to claim 1, wherein the rough surface comprises a surface roughness of more than 500 nm (Day; Figs 1-3; land 16/top surface 25; Day [0017] states that the term “rough” refers to a surface having and R measurement “greater than about 3 microns” i.e. greater than 500 nm); and/or wherein the smooth surface comprises a surface roughness of less than 500 nm.
Regarding Claim 3 – Chamberlin in view of Day teaches the component carrier according to claim 1, wherein the second metal trace comprises rough surface portions and smooth surface portions in an alternating manner (Chamberlin Fig 6; 606/608/610; Chamberlin [0027] states “A first region 606 and a third region 610… are smooth while a second region 608… is rough”).
Regarding Claim 4 – Chamberlin in view of Day teaches the component carrier according to claim 1, wherein the high-frequency signals comprise a frequency of at least 1 GHz (Day [0005] states “High frequency applications… i.e. one GHz and above”).
Regarding Claim 6 – Chamberlin in view of Day teaches the component carrier according to claim 1, wherein only the second metal trace is at least partially covered by a protection layer (Day [0029] teaches applying a permanent resin mask “covering only those areas that are to remain smooth”; Chamberlin teaches that the second metal trace is the smooth trace, while the adjacent first metal trace comprises the rough surface).
Regarding Claim 8 – Chamberlin in view of Day teaches the component carrier according to claim 1, further comprising: a resin layer structure arranged on top of the first metal trace (Chamberlin [0029]), and/or a non-resin layer structure arranged on top of the second metal trace.
Regarding Claim 11 – Chamberlin in view of Day teaches the component carrier according to claim 1, comprising at least one of the following features: wherein the second metal trace comprises the smooth surface at the top portion, while at least one sidewall portion comprises a rough surface; and/or wherein the second metal trace comprises the smooth surface at at least one sidewall, while the top portion comprises a rough surface (Day; Figs 1-3; signal line 14/land 16, side surfaces 20, 22, top surface 25; Day [0017]); wherein the component carrier comprises a peripheral portion and a central portion, and wherein the surface roughness of first metal traces at the peripheral portion of the component carrier is larger than the surface roughness of first metal traces at the central portion of the component carrier; wherein at least one first metal trace is larger than the adjacent second metal trace, wherein the at least one first metal trace is non-functional.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chamberlin et al. (US 20080142249 A1) in view of Day et al. (US 20040007313 A1) and in further view of Harkness et al. (US 20160174364 A1)
Regarding Claim 5 – Chamberlin in view of Day teaches the component carrier according to claim 1, but does not explicitly disclose wherein the first metal trace and the second metal trace are embedded in a common encapsulation material.
Harkness teaches the first metal trace and the second metal trace are embedded in a common encapsulation material (Harkness claim 62 states “an insulating matrix; a plurality of conductive layers embedded in the insulating matrix” wherein the conductive layers comprise “routing layers with signal traces”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Chamberlin in view of Day with the first metal trace and the second metal trace are embedded in a common encapsulation material as taught by Harkness because Harkness teaches that roughened regions provide “adequate adhesion for joining multiple layers of a multilayer PCB, and preventing delamination”, while smoothed regions reduce signal loss through the circuit traces (Harkness [0054]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chamberlin et al. (US 20080142249 A1) ) in view of Day et al. (US 20040007313 A1) and in further view of Brist et al. (US 20070154155 A1)
Regarding Claim 9 – Chamberlin in view of Day teaches the component carrier according to claim 1, but does not explicitly disclose comprising at least one of the following features: an adhesion promotor arranged between the non-resin layer structure and the second metal trace, wherein the adhesion promoter comprises polyimide, PI; a further second metal trace arranged on top of the non-resin layer structure and/or on top of the cavity, such that the non-resin layer structure or the cavity functions as a waveguide.
Brist teaches a further second metal trace arranged on top of the non-resin layer structure and/or on top of the cavity (Fig 3; 342; Brist [0054]), such that the non-resin layer structure or the cavity functions as a waveguide (Brist [0022] states “a channel is formed in printed circuit board material… to form… an embedded waveguide” and [0045] states “a channel, trench, and/or cavity are formed”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Chamberlin in view of Day with a further second metal trace arranged on top of the non-resin layer structure and/or on top of the cavity, such that the non-resin layer structure or the cavity functions as a waveguide as taught by Brist because Brist [0006] states “In order to ensure a minimal loss and to guide the energy of such high frequencies, one solution might be to use waveguide structures”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADITYA SHARMA whose telephone number is (571)270-7246. The examiner can normally be reached Monday - Friday 8:30 - 5:30.
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/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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