DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. Applicant’s amendment to the claims, filed on July 8th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
3. Applicant’s arguments/remarks, see pgs. 6-11, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
Pertaining to the Applicant’s arguments/remarks, pgs. 6-11, regarding the cited figure of Fig. 18H being an intermediate structure:
The Examiner notes that the intermediate structure are referred to in the prior art because of the clear labeling and descriptions which are not repeated for the final semiconductor device product. See prior art S1 [0161] “FIGS. 18A-18I illustrate the formation of the pillar select device at the BEOL (top) portion of 3D memory shown in FIG. 17 at various processing stages.” The elements which are corresponded to the claimed limitations are part of the final semiconductor device product.
With regards to the Applicant’s arguments directed towards a gap and single n+ doping process illustrated in Applicant’s Fig. 12:
It is noted that the features upon which applicant relies are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Therefore, the Examiner disagrees that the claims as currently amended overcome the prior art(s) of record.
Note by the Examiner
4. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claim(s) 1-5 are rejected under 35 U.S.C. 102(a1)&(a2) as being anticipated by Scheuerlein (US 2012/0147646 A1), hereinafter as S1
6. Regarding Claim 1, S1 discloses (see Figs. 11-12, 17, 18A-18I) a semiconductor memory underlying circuit (see [0161] “pillar select device at the BEOL (top) portion of 3D memory shown in FIG. 17”), comprising a row line layer (see Fig. 18A layer of element 673, and see [0162] “layer 673 of N+ poly”), a column line layer (layer of element 672, see [0162] “gate material layer 672”) located above the row line layer (see Fig. 17,18I), and an insulating isolation layer (element 670, see [0162] “oxide layer 670”) between the row line layer and the column line layer (see Fig. 17), wherein a predetermined number of row lines (see Fig. 18G a plurality of openings in the three dimensional view having pillar gate structuring, and Fig. 17 and [0160] “FIG. 17 shows another embodiment of a memory system that includes vertical bit lines … on each side of a vertical bit line 680 are sets of word lines 682” and see Figs. 11-12 the memory system can include an array such that there are a plurality of row line layers in a three dimensional view) made of a doped semiconductor material (N+ polysilicon) are provided inside the row line layer, and a predetermined number of column lines made of a conductive material (N+ polysilicon) are provided inside the column line layer (see Figs. 11-12, 17 and [0160] The column lines are also formed in a three dimensional array), with directions of the row lines and the column lines being perpendicular to each other (see Fig. 18G), the lower segment (see Fig. 18I element p- segment of element 712 in between the two n+ regions) of the MOS hole is a channel region (see [0166] “pillar holes being filled with P- polysilicon, which is a suitable channel material”), and the row line functions as a drain electrode (see [0170] “FIG. 18I illustrates the formation of the drain of the pillar select device. The p-polysilicon filling the pillar hole has its bottom end doped with n+ to form the drain”); metal oxide semiconductor (MOS) holes (holes containing elements 710, 712, see [0164] “gate oxide layer 710 followed by a polysilicon layer 712” and [0171] “Thus, between each local bit line pillar and the metal line is formed a pillar select device in the form of a npn MOS thin film transistor controlled by a row select line 672.”) penetrating the column line layer and the insulating isolation layer are provided at intersections of the row lines and column lines (see Fig. 18G,H; further, note the claims do not require the row lines and column lines to be separated and physically isolated such that they can be divided into line regions which have intersections at which MOS holes are formed);
an upper segment (see Fig. 18H element “n+” section of element 712) and a lower segment (element “p-“ section of element 712) of the MOS hole both are filled with conductive materials (doped polysilicon);
the semiconductor material in the upper segment of the MOS hole has a doping type the same as that of the row line (n+ doping);
the semiconductor material in the lower segment of the MOS hole has a doping type opposite to that of the row line (p-type doping) and is in contact with the row line (see Fig. 17); the semiconductor materials in the upper and lower segments are in direct contact with each other (see Fig. 17); and the semiconductor material filled in the MOS hole is isolated from an inner wall of the MOS hole by an insulating layer (element 710, see [0164] “gate oxide layer 710”).
7. Regarding Claim 2, S1 discloses the semiconductor memory underlying circuit according to claim 1, wherein the MOS holes are rectangular (see Fig. 18G).
8. Regarding Claim 3, S1 discloses the semiconductor memory underlying circuit according to claim 1, wherein the column lines are made of a doped semiconductor material (see [0162] “The gate material layer 672 is, for example, metal, Titanium Nitride or doped polysilicon” Selected as doped polysilicon).
9. Regarding Claim 4, S1 discloses a preparation method for a semiconductor memory underlying circuit (see Figs. 11-12, 17, 18A-18I and [0161] “pillar select device at the BEOL (top) portion of 3D memory shown in FIG. 17”), comprising the following steps:
(1) setting a row line layer (see Fig. 18A layer of element 673, and see [0162] “layer 673 of N+ poly”) on a bottom basic circuit layer (see Fig. 18A CMOS layer), wherein the row line layer has a predetermined number of parallel row lines (see Fig. 18G a plurality of openings in the three dimensional view having pillar gate structuring, and Fig. 17 and [0160] “FIG. 17 shows another embodiment of a memory system that includes vertical bit lines … on each side of a vertical bit line 680 are sets of word lines 682” and see Figs. 11-12 the memory system can include an array such that there are a plurality of row line layers in a three dimensional view) made of a doped semiconductor material (N+ polysilicon);
(2) covering the row line layer with an insulating isolation layer (see Fig. 18A element 670, see [0162] “oxide layer 670”), and then setting a column line layer (layer of element 672, see [0162] “gate material layer 672”) on the insulating isolation layer (see Fig. 17,18I), wherein the column line layer has a predetermined number of parallel column lines perpendicular to the row lines (see Fig. 18G a plurality of openings in the three dimensional view having pillar gate structuring, and Fig. 17 and [0160] “FIG. 17 shows another embodiment of a memory system that includes vertical bit lines … on each side of a vertical bit line 680 are sets of word lines 682” and see Figs. 11-12 the memory system can include an array such that there are a plurality of row line layers in a three dimensional view), and the column lines are made of a conductive material (N+ polysilicon);
(3) forming holes (holes containing elements 710, 712, see [0164] “gate oxide layer 710 followed by a polysilicon layer 712” and [0171] “Thus, between each local bit line pillar and the metal line is formed a pillar select device in the form of a npn MOS thin film transistor controlled by a row select line 672.”) at intersections of the row lines and the column lines (see Fig. 18G,H; further, note the claims do not require the row lines and column lines to be separated and physically isolated such that they can be divided into line regions which have intersections at which MOS holes are formed), wherein the holes penetrate the column line layer and the insulating isolation layer (see Fig. 17, 18I), a bottom of the hole exposes the row line (see Fig. 18B), and an opening of the hole is located on an upper surface of the column line layer (see Fig. 18B);
(4) coating an inner wall of the hole with an insulating dielectric material (see Fig. 18C element 710, see [0164] “gate oxide layer 710”), and then removing the insulating dielectric material at the bottom of the hole, to expose the row line at the bottom of the hole (see Fig. 18D and [0165]); and
(5) filling a lower segment of the hole with a semiconductor material of a doping type opposite to that of the row line (see Fig. 18E-F portion of element “p-“ below a lower boundary of element “n+” and see [0166]), and then filling the rest of the hole with a semiconductor material of a doping type the same as that of the row line (see Fig. 18F element “n+” and see [0167]; note, the filling is performed by adding the doping type the same as the row line in the rest of the hole in the same manner as the Applicant’s invention – see Applicant’s Fig. 11 the entirety of the hole is filled first with the doping type opposite to that of the row line and then see Fig. 12 the rest of the hole is filled with the row line doping type), wherein the lower segment (see Fig. 18I element p- segment of element 712 in between the two n+ regions) of the MOS hole is a channel region (see [0166] “pillar holes being filled with P- polysilicon, which is a suitable channel material”), and the row line functions as a drain electrode (see [0170] “FIG. 18I illustrates the formation of the drain of the pillar select device. The p-polysilicon filling the pillar hole has its bottom end doped with n+ to form the drain”)
10. Regarding Claim 5, S1 discloses the preparation method for a semiconductor memory underlying circuit according to claim 4, further comprising the following steps:
connecting each row line and each column line to the bottom basic circuit layer (see Fig. 18A connection through element 674 and element “Metal Layers” to the CMOS and see [0144] “global bit line such as GBL 250 is formed below the vertically oriented select device, in the FEOL as part of the metal layer-1 or metal layer-2 502”)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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