DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo (US 2022/0100088).
Kuo discloses metal-comprising resist layers such as metal oxide resist layers, methods for forming the resist layer and lithography methods that implement the metal-comprising resist layer. Kuo discloses details and illustrates various embodiments of the method. (Figure 1A-1C). Kuo discloses lithography processes, such as a lithography process A and a lithography process B, use metal oxide resist layers to improve lithography pattern fidelity. (Para, 0019). Kuo discloses process B is a cyclic metal resist deposition process used to form the metal oxide resist layer in lithography process. (Para, 0019; Fig. 1A-1C). Kuo also illustrates top views of workpieces after deposition and after patterning of the metal oxide resist layers used in lithography process A and lithography process B. (Para, 0019; Fig. 1A-1C).
Kuo discloses the process starts with providing a workpiece 10, which is at an intermediate stage of fabrication of an IC device, where workpiece 10 undergoes lithography process A or lithography process B. (Para, 0019). Kuo discloses the workpiece 10 includes a wafer 15 and a material layer 20 to be processed (also referred to herein as an underlying layer) disposed over wafer 15, which includes a substrate (for example, a semiconductor substrate), a mask (also referred to as a photomask or reticle), or any base material on which processing may be conducted to provide layers of material to form various features of an IC device. (Para, 0020; Fig. 1A-1C). Kuo explains that depending on IC fabrication stage, wafer 15 includes various material layers configured to form IC features. (Para, 0020; Fig.1A-1C).
Kuo discloses both lithography process A and B begin with depositing a metal oxide resist layer having a target thickness T over material layer 20, such as a metal oxide resist layer 30 in lithography process A and a metal oxide resist layer 40 in lithography process B. (Para, 0021; Fig. 1A-1C). Kuo discloses both metal oxide resist layer 30 and 40 are sensitive to radiation used during a lithography exposure process, such as deep ultraviolet (DUV) radiation, EUV radiation, e-beam radiation, ion beam radiation, and/or other suitable radiation. (Para, 0021). Kuo explains in some embodiments, metal oxide resist layer 30 and metal oxide resist layer 40 are sensitive to radiation having a wavelength less than about 13.5 nm and both metal oxide resist layer 30 and metal oxide resist layer 40 each include a metal-and-oxygen comprising radiation sensitive material, where the metal is hafnium, titanium, zirconium, tantalum, tin, lanthanum, indium, antimony, other metal constituent that facilitates absorption of radiation (e.g., EUV radiation) and/or resistance to an IC process used during fabrication of workpiece 10 (e.g., etching), or combinations thereof. (Para, 0021).
Kuo discloses in some embodiments, metal oxide resist layer 30 and/or metal oxide resist layer 40 can include other resist components that facilitate absorption of radiation and/or crosslinking reactions upon exposure to radiation, such as photoacid generator (PAG) component, thermal acid generator (TAG) component, photo-decomposable base (PDB) component, other suitable resist component, or combinations thereof. (Para, 0021). Moreover, Kuo discloses in some embodiments, before depositing metal oxide resist layer 30 and/or metal oxide resist layer 40, an ARC layer is formed over material layer 20, such that metal oxide resist layer 30 and/or metal oxide resist layer 40 are deposited on the ARC layer. (Para, 0021).
Kuo discloses metal oxide resist layer 30 and metal oxide resist layer 40 are formed by different deposition processes, which results in metal oxide resist layer 30 and metal oxide resist layer 40 having different characteristics that impact pattern fidelity. (Para, 0022). Kuo discloses in lithography process A, metal oxide resist layer 30 is blanket deposited over material layer 20 by a chemical vapor deposition (CVD) process. (Para, 0022). Kuo discloses this CVD process may be a plasma enhanced CVD (PECVD), remote PECVD (RPECVD) process, a metal-organic CVD (MOCVD) process, a low-pressure CVD (LPCVD) process, ultrahigh vacuum CVD (UHVCVD) process, a sub-atmospheric pressure CVD (SACVD) process, a laser-assisted CVD (LACVD) process, an aerosol-assisted CVD (AACVD) process, atomic layer CVD (ALCVD), other suitable CVD process, or combinations thereof. (Para, 0022). Kuo discloses metal oxide resist layer 30 having thickness T can also be blanket deposited over material layer 20 by an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or other suitable deposition process. (Para, 0022). These disclosures and the disclosures of Kuo as discussed above teach the limitation of claim 1, ‘A production method for a semiconductor substrate, the method comprising: performing a vapor deposition of a metal compound or metal directly or indirectly onto a substrate to form a metal-containing resist film…wherein the metal compound or metal comprises an Au atom, a Cr atom, an Ag atom, an In atom or a combination thereof.’ These disclosures also teach the limitation of claims 3 and 9.
Kuo discloses with lithography process B, a cyclic metal resist deposition process forms metal oxide resist layer 40 having a substantially uniform density from bottom to top, such as from a bottom surface of metal oxide layer 40 (e.g., interfacing with material layer 20) to a top surface of metal oxide resist layer 40. (Para, 0025). Kuo explains this cyclic metal resist deposition process forms metal oxide resist sublayers 40A-40D, which combine to form metal oxide resist layer 40 having thickness T, where a sum of thicknesses t1-t4 is equal to target thickness T. (Para, 0025). Kuo discloses in some embodiments, deposition processes are CVD processes and in some embodiments, deposition processes are ALD processes. (Para, 0027).
Kuo discloses after loading workpiece 10 having material layer 20 disposed over wafer 15 in a process chamber, each deposition processes can include heating workpiece 10 to a desired temperature (e.g., a temperature that facilitates chemical reactions needed to form metal-and-oxygen comprising resist material over material layer 20), flowing one or more deposition precursors and/or carriers into the process chamber, where the deposition precursors react and/or decompose to form a metal-and-oxygen comprising resist material over material layer 20, and purging any remaining deposition precursors (e.g., unreacted deposition precursors), carriers, and/or byproducts from the process chamber. (Para, 0027). Kuo explains, each position processes has at least one deposition phase and at least one purge phase and the metal-and-oxygen comprising resist material accumulates on material layer 20 during the deposition phase, which is performed until the metal-and-oxygen comprising resist material accumulated over material layer 20 has a desired thickness. (Para, 0027).
Kuo discloses, during the deposition phase, the deposition precursors can react with one another, material layer 20, metal-and-oxygen comprising resist material accumulating on material layer 20, and/or byproducts of chemical reactions thereof to form metal oxide resist sublayers 40A-40D. (Para, 0027). Kuo discloses the deposition precursors include a metal-containing precursor, a reaction gas, and/or a carrier, where the metal-containing precursor includes MaRbXc, where 1≤a≤2, b≥1, and c≥1 and in some embodiments, b+c≤5. (Para, 0027). Kuo discloses M can be Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, or Lu. (Para, 0027). Kuo discloses, R can be a substituted alkyl group, a substituted alkenyl group, a substituted carboxylate group, an unsubstituted alkyl group, an unsubstituted alkenyl group, or an unsubstituted carboxylate group and X can be a halide group or a sulfonate group. (Para, 0027). These disclosures teach the limitation of claims 4-7 and 10-13.
Kuo discloses that after depositing metal oxide resist layer 30 and metal oxide resist layer 40, lithography process A and lithography process B proceed with exposure processes, which expose metal oxide resist layer 30 and metal oxide resist layer 40 to patterned radiation. (Para, 0036). Kuo discloses the patterned radiation may have a wavelength less than about 250 nm, such as DUV radiation, EUV radiation, and/or other suitable radiation. (Para, 0036). Kuo discloses the patterned radiation is EUV radiation, such as radiation having a wavelength less than about 13.5 nm. (Para, 0036; Fig. 1A-1C). These disclosures and illustrations teach the limitation of claim 1, ‘ A production method for a semiconductor substrate, the method comprising: …and a step of exposing the metal-containing resist film to light…’ and the limitation of claims 8 and 14-16.
Kuo discloses a mask 60 having an IC pattern defined therein is used to provide patterned radiation that can form an image of the IC pattern on metal oxide resist layer 30 and metal oxide resist layer 40. (Para, 0036; Fig.1A-1C). Kuo explains the mask 60 blocks, transmits, and/or reflects radiation to metal oxide resist layer 30 and metal oxide resist layer 40 depending on a mask pattern of mask 60 and/or mask type (for example, binary mask, phase shift mask, or EUV mask). (Para, 0036; Fig. 1A-1C). Kuo also discloses the exposure process can be performed in air, liquid (immersion lithography), or vacuum (for example, when exposing workpiece 10 to EUV radiation and/or e-beam). In some embodiments, the exposure process directly modulates radiation, such as an electron beam (e-beam) or an ion beam, according to an IC pattern without using a mask, such as mask 60. (Para, 0036; Fig.1A-1C).
Kuo discloses that lithography processes A and B each proceed with performing a developing process on metal oxide resist layer 30 and metal oxide resist layer 40, thereby forming a patterned metal oxide resist layer 30′ and a patterned metal oxide resist layer 40′, respectively. (Para, 0038; Fig. 1A-1C). Kuo explains, the developing processes dissolve exposed (or non-exposed) portions of metal oxide resist layer 30 and metal oxide resist layer 40 depending on characteristics of metal oxide resist layer 30 and metal oxide resist layer 40, respectively, and characteristics of a developing solution used in the developing process. (Para, 0038). These disclosures teach the limitation of claim 2.
Therefore, the limitation of claims 1-16 are anticipated by the disclosures and illustrations of Kuo as discussed above.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
