DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 23 is objected to because of the following informalities: line 11 recites “undelying”, but appears it should recite “underlying”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitation “the silicon-containing clogging material” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. It appears the claim should depend from claim 21.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-8, 10-11, 13-14, 17-19, and 21 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Tahara et al. (US 20140206198 A1).
As to claim 1, Tahara discloses a method of etching a material on a semiconductor substrate [Abstract], the method comprising:
(a) providing a semiconductor substrate having an exposed layer of a mask material [para. 0027; Fig. 4], a recessed feature 2, and a layer of a target material underlying the layer of the mask material [Fig. 4], wherein the target material is exposed at the bottom of the recessed feature [para. 0027; Fig. 4];
(b) etching the target material using a plasma etch [para. 0027; Fig. 4], and thereby increasing depth of the recessed feature [Fig. 4], wherein the etching of the target material results in narrowing or blocking of the recessed feature at least at one location due to deposition of a clogging material 6 [para. 0027, “On sidewall portions of the patterns and in the trenches (STI) 4, a deposit 6 is adhering”; para. 0033; Fig. 4]; and
(c) etching the clogging material by contacting the semiconductor substrate with a halogen source and a vapor of a liquid selected from the group consisting of an organic solvent and water [para. 0036-42].
As to claim 3, Tahara discloses the method of claim 1, wherein the clogging material comprises silicon oxide [para. 0027, “a deposit of a silicon oxide”].
As to claim 4, Tahara discloses the method of claim 1,wherein the target material is selected from the group consisting of carbon and silicon [para. 0027].
As to claim 5, Tahara discloses the method of claim 1,wherein the mask material is selected from the group consisting of silicon oxynitride, silicon nitride, silicon oxide [para. 0027, gate oxide film 2], silicon oxycarbide, silicon boride, boron-doped carbon, tungsten, tungsten-doped carbon, and boron-doped carbon.
As to claim 6, Tahara discloses the method of claim 1, wherein the etching of the clogging material has an etch selectivity of greater than 1 to both the mask material and the target material [para. 0053].
As to claim 7, Tahara discloses the method of claim 1, wherein the etching of the clogging material is performed in an absence of plasma [para. 0036-42].
As to claim 8, Tahara discloses the method of claim 1, wherein the etching of the clogging material comprises activating at least one reactant in a plasma without externally biasing the semiconductor substrate [para. 0042-44].
As to claim 10, Tahara discloses the method of claim 1,wherein the etching of the clogging material comprises simultaneously contacting the semiconductor substrate with the halogen source and the vapor of a liquid selected from the group consisting of the organic solvent and water [para. 0036-42].
As to claim 11, Tahara discloses the method of claim 1,wherein the etching of the clogging material comprises sequentially contacting the semiconductor substrate with the halogen source and the vapor of a liquid selected from the group consisting of the organic solvent and water [para. 0085].
As to claim 13, Tahara discloses the method of claim 1, wherein the etching of the clogging material is conducted at a pressure of between about 0.01 - 10 Torr [para. 0040] and a temperature of between about -60 - 250 °C [para. 0040].
As to claim 14, Tahara discloses the method of claim 1, wherein the recessed feature 2 of the semiconductor substrate provided in (a) has a width of about 5 - 300 nm [para. 0003; para. 0027; here, shallow trench isolation structures conventionally have a trench width of about 140 nm].
As to claim 17, Tahara discloses the method of claim 1, wherein the solvent is selected from the group consisting of an alkane, a ketone, and an alcohol [para. 0037; para. 0085].
As to claim 18, Tahara discloses the method of claim 1, wherein the halogen source is selected from the group consisting of nitrogen tribromide (NBr3). nitrogen trichloride (NCl3), chlorine trifluoride (ClF3), hydrogen fluoride (HF) [para. 0037], hydrogen chloride (HCl), and hydrogen bromide (HBr).
As to claim 19, Tahara discloses the method of claim 1, wherein the plasma etch in (b) comprises contacting the substrate with an oxygen-containing reactant [para. 0028].
As to claim 21, Tahara discloses a method of etching a material on a semiconductor substrate [Abstract], the method comprising:
(a) providing a semiconductor substrate having an exposed layer of a mask material [para. 0027; Fig. 4], a recessed feature 2, and a layer of a target material underlying the layer of the mask material [Fig. 4], wherein the target material is exposed at the bottom of the recessed feature [para. 0027; Fig. 4], wherein the mask material is a silicon-containing material [para. 0027, “polysilicon film 1”], and wherein the target material is selected from the group consisting of carbon (C) and silicon (Si) [para. 0027, silicon wafer];
(b) etching the target material using an oxygen-containing plasma etch [para. 0027; Fig. 4], and thereby increasing depth of the recessed feature [Fig. 4], wherein the etching of the target material results in narrowing or blocking of the recessed feature at least at one location due to deposition of a silicon-containing clogging material 6 [para. 0027, “On sidewall portions of the patterns and in the trenches (STI) 4, a deposit 6 is adhering”; para. 0033, “a silicon oxide (for example, SiO.sub.2 or SiOBr) being the deposit deposited on the sidewalls of the patterns”; Fig. 4]; and
and (c) etching the silicon-containing clogging material 6 by contacting the semiconductor substrate with a halogen source and a vapor of a liquid selected from the group consisting of an organic solvent and water [para. 0036-42].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15, 20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Tahara et al. (US 20140206198 A1), as applied to claims 1, 3-8, 10-11, 13-14, 17-19, and 21 above in view of Shih (US 20090243030 A1).
As to claim 15, Tahara discloses the method of claim 1, but fails to explicitly disclose:
wherein the semiconductor substrate comprises a device selected from the group consisting of a partially fabricated 3D NAND device, a DRAM device, and a logic device.
However, Shih teaches that shallow trench isolation (STI) structures are conventionally used in logic devices [Abstract; para. 0019], and therefore it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an STI, of Tahara, to include forming a logic device from the formed STI, as taught by Shih [Abstract; para. 0119].
As to claim 20, Tahara discloses the method of claim 1, but fails to explicitly disclose:
the steps of:
applying photoresist to the semiconductor substrate;
exposing the photoresist to light;
patterning the photoresist and transferring the pattern to the semiconductor substrate; and
selectively removing the photoresist from the semiconductor substrate.
However, Shih teaches forming a photoresist, patterning the photoresist, patterning the underlying substrate, and removing the photoresist are conventional steps in forming an STI [para. 0019; Fig. 1A], therefore would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming the polysilicon and oxide gate pattern, to include forming a photoresist, patterning the underlying STI feature, and removing the photoresist, of Shih, as is conventional in the art and as taught by Shih [Abstract; para. 0119; Fig. 1A].
As to claim 22, modified Tahara discloses the method of claim 20, wherein the silicon-containing clogging material is silicon oxide [para. 0027; para. 0033].
Claims 2, 9, 16, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Tahara et al. (US 20140206198 A1), as applied to claims 1, 3-8, 10-11, 13-14, 17-19, and 21 above, in view of Zhu et al. (KR 20210011493 A, Machine Translation).
As to claim 2, Tahara discloses the method of claim 1, but fails to explicitly disclose:
wherein etching of the target material (b) and etching of the clogging material (c) are performed in one processing chamber.
However, Zhu et al. discloses an efficient cleaning and etching apparatus [Abstract; Background; Fig. 6a], which permits plasma etching, to form semiconductor patterns, and semiconductor etch cleaning, including supplying vapor of HF and alcohol [Fig. 6b], and cyclical etching/cleaning cycles thereof [claim 10] to achieve high aspect ratios feature having an aspect ratio of at least 5:1 [claim 6] comprising:
(b) a plasma generating mechanism 670 [Fig. 6a; pg. 6, para. 6];
(c) a mechanism for vaporising a liquid connected with the process chamber and configured for delivering the liquid to the process chamber [Fig. 6b; pg. 6, para. 9].
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of etching a semiconductor pattern and cleaning the pattern using a vapor of HF and alcohol in two separate apparatus, of Zhu, to include performing the plasma etching and vapor cleaning within a single apparatus, of Zhu, in order to improve process throughput, as taught by Zhu [Abstract; Background].
As to claim 9, Tahara discloses the method of claim 1, but fails to explicitly disclose:
repeating steps (b) - (c).
However, Zhu et al. discloses an efficient cleaning and etching apparatus [Abstract; Background; Fig. 6a], which permits plasma etching, to form semiconductor patterns, and semiconductor etch cleaning, including supplying vapor of HF and alcohol [Fig. 6b], and cyclical etching/cleaning cycles thereof [claim 10] to achieve high aspect ratios feature having an aspect ratio of at least 5:1 [claim 6] comprising:
(b) a plasma generating mechanism 670 [Fig. 6a; pg. 6, para. 6];
(c) a mechanism for vaporising a liquid connected with the process chamber and configured for delivering the liquid to the process chamber [Fig. 6b; pg. 6, para. 9].
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of etching a semiconductor pattern and cleaning the pattern using a vapor of HF and alcohol in two separate apparatus, of Zhu, to include performing the plasma etching and vapor cleaning within a single apparatus, of Zhu, in order to improve process throughput in etching and cleaning, and further to provide cyclic etching/cleaning to achieve high aspect ratio features having an aspect ratio of at least 5:1, as taught by Zhu [Abstract; Background].
As to claim 16, Tahara discloses the method of claim 1, but fails to explicitly disclose:
wherein an aspect ratio of the recessed feature after completion of the etching is at least about 5:1 [Zhu, claim 6].
As to claim 23, Tahara discloses an apparatus for processing a semiconductor substrate [Fig. 2], the apparatus comprising:
(a) a process chamber configured for housing the semiconductor substrate [Fig. 2], wherein the process chamber includes a substrate holder 202 configured to hold the semiconductor substrate and an inlet 203/205 configured to admit one or more reactants to the process chamber [para. 0023-24]; and
(d) a controller comprising program instructions configured to effect etching of a material on the semiconductor substrate by causing:
(i) on a semiconductor substrate comprising an exposed layer of a mask material [para. 0027; Fig. 4], a recessed feature 2, and a layer of a target material unde[r]lying the layer of the mask material [Fig. 4], wherein the target material is exposed at a bottom of the recessed feature [para. 0027; Fig. 4], etching of the target material using a plasma etch, and thereby causing an increase in depth of the recessed feature [para. 0027; Fig. 4]; and
(ii) etching of a clogging material deposited during the plasma etch and narrowing or blocking the recessed feature [para. 0027, “On sidewall portions of the patterns and in the trenches (STI) 4, a deposit 6 is adhering”; para. 0033, “a silicon oxide (for example, SiO.sub.2 or SiOBr) being the deposit deposited on the sidewalls of the patterns”; Fig. 4], by causing contact of the semiconductor substrate with a halogen source and a vapor of a liquid selected from the group consisting of an organic solvent and water [para. 0036-42].
Tahara fails to explicitly disclose an apparatus comprising:
(b) a plasma generating mechanism;
(c) a mechanism for vaporising a liquid connected with the process chamber and configured for delivering the liquid to the process chamber.
However, Zhu et al. discloses an efficient cleaning and etching apparatus [Abstract; Background; Fig. 6a], which permits plasma etching, to form semiconductor patterns, and semiconductor etch cleaning, including supplying vapor of HF and alcohol [Fig. 6b], and cyclical etching/cleaning cycles thereof [claim 10] to achieve high aspect ratios feature having an aspect ratio of at least 5:1 [claim 6] comprising:
(b) a plasma generating mechanism 670 [Fig. 6a; pg. 6, para. 6];
(c) a mechanism for vaporising a liquid connected with the process chamber and configured for delivering the liquid to the process chamber [Fig. 6b; pg. 6, para. 9].
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of etching a semiconductor pattern and cleaning the pattern using a vapor of HF and alcohol in two separate apparatus, of Zhu, to include performing the plasma etching and vapor cleaning within a single apparatus, of Zhu, in order to improve process throughput, as taught by Zhu [Abstract; Background].
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 12, the prior art of record, alone or in combination, fails to teach or suggest the method of claim 1,
“wherein (c) further comprises contacting the semiconductor substrate with an additive selected from the group consisting of an amine, a heterocyclic compound, and a bifluoride source.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: The additionally cited references are cited to show methods and apparatus for removing etching residue or byproducts by contacting the semiconductor with hydrogen fluoride, water vapor, and/or an organic solvent [Abstracts].
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/CHRISTOPHER REMAVEGE/Examiner, Art Unit 1713
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