Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 17, 2024 was filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations “a first semiconductor film made of an oxide semiconductor,” on page 3 lines 7-8 and “each of the plurality of first thin film transistors including a first semiconductor layer formed of the first semiconductor film,” on page 3 lines 21-22. These limitations render the claim indefinite because both the first semiconductor film made of an oxide semiconductor and the first semiconductor layers formed of the first semiconductor film are not included in the display device. The examiner notes that the first semiconductor film made of an oxide semiconductor was fabricated into the first semiconductor layers for the thin film transistors during manufacture of the thin film transistors, and thus, the first semiconductor film made of an oxide semiconductor is not included the display device. For examination purposes, claim 1 will interpreted as requiring each of the plurality of first thin film transistors including a first semiconductor layer formed of the first semiconductor film.
Claims 2-10 are also rejected for containing the same limitations because claims 2-10 depend from claim 1.
Claim 1 recites the limitations “a first metal film,” on page 3 line 9 and “a plurality of first wiring lines formed of the first metal film,” on page 3 line 14. These limitations render the claim indefinite because both the first metal film and the plurality of first wiring lines formed of the first metal film are not included in the display device. The examiner notes that the first metal film was fabricated into the plurality of first wiring lines during manufacture of the plurality of first wiring lines, and thus, the first metal film is not included the display device. For examination purposes, claim 1 will interpreted as requiring a plurality of first wiring lines formed of the first metal film.
Claims 2-10 are also rejected for containing the same limitations because claims 2-10 depend from claim 1.
Claim 1 recites the limitations “a second metal film,” on page 3 line 10 and “a plurality of second wiring lines formed of the second metal film,” on page 3 line 16. These limitations render the claim indefinite because both the second metal film and the plurality of second wiring lines formed of the second metal film are not included in the display device. The examiner notes that the second metal film was fabricated into the plurality of second wiring lines during manufacture of the plurality of second wiring lines, and thus, the second metal film is not included the display device. For examination purposes, claim 1 will interpreted as requiring a plurality of first wiring lines formed of the first metal film.
Claims 2-10 are also rejected for containing the same limitations because claims 2-10 depend from claim 1.
Claim 1 recites the limitation “wherein the protective insulating film includes a thin film portion provided at a portion where the plurality of first wiring lines and the plurality of second wiring lines intersect with each other, and being thinner than a portion of the protective insulating film around the portion of intersection,” on page 3 lines 23-26. This limitation renders the claim indefinite because it is unclear how the protective insulating film includes a thin film portion at a portion where the plurality of first wiring lines and the plurality of second wiring lines intersect with each other because there are multiple places where the plurality of first wiring lines and the plurality of second wiring lines intersect. For examination purposes, this limitation will be interpreted as reciting wherein the protective insulating film includes a thin film portion provided at each portion where the plurality of first wiring lines and the plurality of second wiring lines intersect with each other, and each thin film portion being thinner than a portion of the protective insulating film around that portion of intersection.
Claims 2-10 are also rejected for containing the same limitations because claims 2-10 depend from claim 1.
Claim 2 recites the limitation “wherein the first interlayer insulating film includes a thin film portion provided at a portion where the plurality of first wiring lines and the plurality of second wiring lines intersect with each other, and being thinner than a portion of the first interlayer insulating film around the portion of intersection,” on page 3 lines 30-33. This limitation renders the claim indefinite because it is unclear how the first interlayer insulating film includes a thin film portion at a portion where the plurality of first wiring lines and the plurality of second wiring lines intersect with each other because there are multiple places where the plurality of first wiring lines and the plurality of second wiring lines intersect. For examination purposes, this limitation will be interpreted as reciting wherein the first interlayer insulating film includes a thin film portion provided at each portion where the plurality of first wiring lines and the plurality of second wiring lines intersect with each other, and each thin film portion being thinner than a portion of the first interlayer insulating film around that portion of intersection.
Claims 3 and 9-10 are also rejected for containing the same limitations because claims 3 and 9-10 depend from claim 2.
Claim 3 recites the limitation “a first gate electrode formed of the first metal film,” on page 4 line 8 and claim 1, which claim 3 depends from, recites “a first metal film,” on page 3 line 9. These limitations render claim 3 indefinite because both the first metal film and the first gate electrode formed of the first metal film are not included in the display device. The examiner notes that the first metal film was fabricated into the first gate electrode during manufacture of the thin film transistors, and thus, the first metal film is not included the display device. For examination purposes, claim 3 will be interpreted as requiring a first gate electrode formed of the first metal film.
Claims 9-10 are also rejected for containing the same limitations because claims 9-10 depend from claim 3.
Claim 3 recites the limitation “a first source electrode and a first drain electrode, both of which are formed of the second metal film,” on page 4 lines 11-12 and claim 1, which claim 3 depends from, recites “a second metal film,” on page 3 line 10. These limitations render claim 3 indefinite because both the second metal film and the first source electrode and the first drain electrode, both of which are formed of the second metal film are not included in the display device. The examiner notes that the second metal film was fabricated into the first source electrode and the first drain electrode during manufacture of the thin film transistors, and thus, the second metal film is not included the display device. For examination purposes, claim 3 will be interpreted as requiring a first source electrode and a first drain electrode, both of which are formed of the second metal film.
Claims 9-10 are also rejected for containing the same limitations because claims 9-10 depend from claim 3.
Claim 3 recites the limitation “the protective insulating film includes a thin film portion provided at a portion connecting the first drain electrode which corresponds and a corresponding first electrode of the plurality of first electrodes in each of the plurality of subpixels, and being thinner than a portion of the protective insulating film around the portion of connection,” on page 4 lines 15-18. This limitation renders the claim indefinite because the claim does not recite what the first drain electrode corresponds to. Additionally, this limitation renders the claim indefinite because it is unclear how the first drain electrode is connected to a first electrode in each of the plurality of subpixels. For examination purposes, the limitation will be interpretated as reciting the protective insulating film includes a thin film portion provided at each portion connecting a first drain electrode of a first thin film transistor of the plurality of first thin film transistors and a corresponding first electrode of the plurality of first electrodes, and being thinner than a portion of the protective insulating film around the portion of connection.
Claims 9-10 are also rejected for containing the same limitation because claims 9-10 depend from claim 3.
Claim 5 recites the limitation “the second semiconductor film,” on page 4 lines 33-34 and claim 4, which claim 5 depends from, recites the limitation “a second thin film transistor including a second semiconductor layer formed of a second semiconductor film made of polysilicon,” on page 4 lines 24-25. These limitations render claim 5 indefinite because both the second semiconductor film and the second semiconductor layer formed of a second semiconductor film are not included in the display device. The examiner notes that the second semiconductor film was fabricated into the second semiconductor layer during manufacture of the second thin film transistor, and thus, the second semiconductor film is not included the display device. For examination purposes, claim 5 will be interpreted as requiring a second thin film transistor including a second semiconductor layer formed of a second semiconductor film made of polysilicon.
Claim 6 is also rejected for containing the same limitation because claim 6 depends from claim 5.
Claim 6 recites the limitation “a second gate electrode formed of the third metal film,” on page 5 line 5 and claim 5, which claim 6 depends from, recites “a third metal film,” on page 4 line 30. These limitations render claim 6 indefinite because both the second gate electrode formed of the third metal film and the third metal film are not included in the display device. The examiner notes that the third metal film was fabricated into the second gate electrode during manufacture of the second thin film transistor. For examination purposes, claim 6 will be interpreted as requiring a second gate electrode formed of the third metal film.
Claim 6 recites the limitation “a second source electrode and a second drain electrode, both of which are formed of the second metal film,” on page 5 lines 7-8 and claim 1, which claim 6 depends from, recites “a second metal film,” on page 3 line 10. These limitations render claim 6 indefinite because both the second source electrode and second drain electrode formed of the second metal film and the second metal film are not included in the display device. The examiner notes that the second metal film was fabricated into the second source electrode and the second drain electrode during manufacture of the second thin film transistor. For examination purposes, claim 6 will be interpreted as requiring a second source electrode and a second drain electrode, both of which are formed of the second metal film.
Claim 7 recites the limitation “wherein the second thin film transistor constitutes a peripheral circuit,” on page 5 line 14. This limitation renders the claim indefinite because it is unclear how one transistor constitutes a circuit. The examiner notes that a circuit is made up of components and an individual component such as a transistor may be part of a circuit but one transistor by itself is not a circuit. For examination purposes, claim 7 will be interpreted as requiring the second thin film transistor to be included in a peripheral circuit.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2019/0206977) in view Yamazaki et al. (US 2003/0025166) further in view of Saitoh (US 2020/0183221).
Regarding Claim 1:
Lee discloses a display device comprising:
a base substrate (substrate, See figs. 4-5, ref. no. 110 and paragraph 63);
a thin film transistor layer which is provided on the base substrate and in which a first semiconductor film (first semiconductor, See fig. 4, ref. nos. 135ab, and paragraphs 65-66), a first gate insulating film made of an inorganic insulating film (gate insulating layer made of silicon oxide, See figs. 4-5, ref. no. 140 and paragraph 71), a first metal film (upper layers of gate lines made of aluminum, See figs. 2-3, ref. no. 121, figs. 4-5, ref. nos. 121, 121q, and paragraph 73) a first interlayer insulating film made of an inorganic insulating film (first interlayer insulating layer made of silicon oxide, See figs. 4-5, ref. no. 160 and paragraph 76), a second film (data lines, See figs. 2-5, ref. no. 171 and paragraph 78), a protective insulating film made of an inorganic insulating film (second interlayer insulating layer made of the same material, silicon oxide, as the first interlayer insulating layer, See figs. 4-5 ref. no. 180), and a flattening film made of an organic resin material (pixel defining layer made of polyimide resin, See figs. 4-5, ref. no. 195 and paragraph 84) are sequentially layered,
the thin film transistor layer including
a plurality of first wiring lines formed of the first metal film (plurality of signal lines, See figs. 2-3, 5, ref. no. 121, paragraphs 54-55), the plurality of first wiring lines extending in parallel with each other (the signal lines substantially extend in a row direction and are substantially parallel to each other, See paragraph 55),
a plurality of second wiring lines formed of the second film (plurality of data lines, See figs. 2-3, 5, ref. no. 171, paragraphs 54-55), the plurality of second wiring lines extending in parallel with each other in a direction intersecting with the plurality of first wiring lines (the data lines substantially extend in a column direction and are substantially parallel to each other, See paragraph 55), and
a plurality of first thin film transistors (switching transistors, See fig. 2, ref. no. Qs, fig. 4, ref. nos. 135a, 154a, paragraphs 56-58, 62, 65-66, 72) provided corresponding to a plurality of subpixels (the OLED displaying one of the three primary colors, red, green, blue, causes the driving circuit shown in figure 2 to considered a subpixel driving circuit, See fig. 2, ref. no. LD and paragraph 60) constituting a display region (the subpixel driving circuits are used for displaying an image, thus, a region containing the subpixel driving circuit is a display region, See paragraph 60), and
each of the plurality of first thin film transistors including a first semiconductor layer (first semiconductor, See fig. 4, ref. nos. 135ab, and paragraphs 65-66) formed of the first semiconductor film.
Lee does not disclose the second film is made of metal, the first semiconductor film is made of an oxide semiconductor and wherein the protective insulating film includes a thin film portion provided at a portion where the plurality of first wiring lines and the plurality of second wiring lines intersect with each other, and being thinner than a portion of the protective insulating film around the portion of intersection.
Yamazaki discloses a first wiring made of aluminum (See figs. 2A-2B, ref. no. 105 and paragraph 87).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Lee to include the second film being made of aluminum as taught by Yamazaki in order to reduce the number of materials used in manufacturing the display device by using the same material in the gate lines and the data lines.
The above stated combination of Lee and Yamazaki does not disclose the first semiconductor film is made of an oxide semiconductor and wherein the protective insulating film includes a thin film portion provided at a portion where the plurality of first wiring lines and the plurality of second wiring lines intersect with each other, and being thinner than a portion of the protective insulating film around the portion of intersection.
Yamazaki discloses flattening a first insulating film covering a wiring layer by removing a portion of the first insulating film covering a wiring layer such that the first insulting film above the wiring layer is thinner than the first insulting film beside the wiring layer (See figs. 2A-2B, ref. nos. 102, 105, and 89-90)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Lee and Yamazaki to include flattening second interlayer insulating layer as taught by Yamazaki in order to flatten surface irregularities. (See Yamazaki paragraph 90.) (The examiner first notes that in Lee the portions of the second interlayer insulating layer above the data line above bumps on the left side and the right side of the recess are provided at a portion where the data line and the gate line intersect because the lower layer of the gate line partial overlaps the flat portion of the data line on these bumps. See Lee fig. 5, ref. nos. O, 121p, 171, 181, and paragraphs 92-93. The examiner now notes that after flattening the top surface of the second interlayer insulating layer the portion of the second interlayer insulating layer above the data line above the bump on the left side is thinner than the portion of the second interlayer insulating layer to the left of the bump and the portion of the second interlayer insulating layer above that data line above the bump on the right side is thinner than the portion of the second interlayer insulating layer to the right of the bump.)
The above stated combination of Lee and Yamazaki does not disclose the first semiconductor film is made of an oxide semiconductor.
Saitoh discloses a thin film transistor having an oxide semiconductor layer (See fig. 1, ref. nos. 12, 20, and paragraph 38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Lee and Yamazaki to include the first semiconductor film is made of an oxide semiconductor as taught by Saitoh in order to reduce power consumption. (See Saitoh paragraph 38.)
Regarding Claim 2:
Lee discloses wherein the first interlayer insulating film includes a thin film portion provided (the portion of the first interlayer insulating layer between the upper layer of the gate line and the flat portion of the data line in the bottom of the recess, See fig. 5, ref. nos. O, 121q, 160, 171, and paragraphs 92-93) at a portion where the plurality of first wiring lines and the plurality of second wiring lines intersect with each other (the gate lines and the data lines overlap, See figs. 3, 5, ref. nos. 121, 171, paragraph 62, 92-93), and being thinner than a portion of the first interlayer insulating film around the portion of intersection (the portion the portion of the first interlayer insulating layer between the upper layer of the gate line and the flat portion of the data line in the bottom of the recess is thinner than the portion of the first interlayer insulating layer to the left of this portion and to the right of this portion, See fig. 5, ref. nos. O, 121q, 160, 171).
Regarding Claim 4:
Lee discloses wherein the thin film transistor layer is provided with a second thin film transistor (driving transistor, See fig. 2, ref. no. Qd, fig. 4, ref. nos. 135b, 154b, paragraphs 56-58, 62, 65-67, 72) including a second semiconductor layer formed of a second semiconductor film made of polysilicon (second semiconductor including polysilicon, See fig. 4, ref. no. 135B and paragraph 65).
Regarding Claim 7:
Lee discloses wherein the second thin film transistor constitutes a peripheral circuit (the driving transistor is included in the circuit for driving the OLED, See fig. 2, ref. no. Qd and paragraphs 56-58).
Regarding Claim 8:
Lee discloses wherein each of the plurality of first wiring lines is a gate line (the gate lines are connected to the gates of the switching transistors, See figs. 2, ref. nos. Qs, 121, fig. 3, ref. no. 121, and paragraph 72), and each of the plurality of second wiring lines is a source line (the data lines are connected to the sources of the switching transistors, See figs. 2, ref. nos. Qs, 171, fig. 3, ref. no. 171, and paragraph 78).
Allowable Subject Matter
Claims 3, 5-6, and 9-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The disclosures and illustrations of Lee, Yamazaki, and Saitoh as discussed above fail to teach or suggest the limitations of claims 3 and 9-10 because Lee, Yamazaki, and Saitoh fail to teach or suggest the display device further comprises a light-emitting element layer which is provided on the thin film transistor layer and in which a plurality of first electrodes, a plurality of light-emitting function layers, and a common second electrode are sequentially layered corresponding to the plurality of subpixels, wherein each of the plurality of first thin film transistors includes the first semiconductor layer in which a first source region and a first drain region are defined to be separated from each other, a first gate electrode formed of the first metal film on the first semiconductor layer with the first gate insulating film interposed between the first semiconductor layer and the first gate electrode, and a first source electrode and a first drain electrode, both of which are formed of the second metal film on the first interlayer insulating film, the first source electrode and the first drain electrode being separated from each other and electrically connected to the first source region and the first drain region, respectively, and the protective insulating film includes a thin film portion provided at a portion connecting the first drain electrode which corresponds and a corresponding first electrode of the plurality of first electrodes in each of the plurality of subpixels, and being thinner than a portion of the protective insulating film around the portion of connection. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Lee, Yamazaki, and/or Saitoh to teach and/or suggest the limitations of claim 3. Therefore, claim 3 and claims 9-10 depending directly therefrom include allowable subject matter.
The disclosures and illustrations of Lee, Yamazaki, and Saitoh as discussed above fail to teach or suggest the limitations of claims 5-6 because Lee, Yamazaki, and Saitoh fail to teach or suggest wherein the thin film transistor layer includes a second gate insulating film made of an inorganic insulating film, a third metal film, a second interlayer insulating film made of an inorganic insulating film, the first semiconductor film, the first gate insulating film, the first metal film, the first interlayer insulating film, the second metal film, the protective insulating film, and the flattening film, all of which are sequentially layered on the second semiconductor film. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Lee, Yamazaki, and/or Saitoh to teach and/or suggest the limitations of claim 5. Therefore, claim 5 and claim 6 depending directly therefrom include allowable subject matter.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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