DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 and its dependents recite “a plurality of light-emitting functional layers, and a second electrode that is common being stacked sequentially.” The examiner cannot ascertain the meaning of the “common” as it is used in this context. As it is recited, the word “common” does not appear be using the ordinary and plain meaning of term1. Does the applicant mean that the stack of layers are common to all subpixels or are the layers in common because they are being stacked? For the purpose of compact prosecution, the examiner will ignore the claim term “common.”
Finally, claim 1 and its dependents recite the limitation of “an edge cover that is common.” It is not clear how the edge cover is common in relation to something. Is it common to all pixels, to all underlying structures of a singular subpixel, or both. For the purpose of compact prosecution, the examiner will cite art that teaches an edge cover that is found on all subpixels.
Regarding claim 2, it recites the limitation "the first semiconductor layer.” There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 7, recites the limitation "the low transmittance portion” that is associated with the edge cover. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear whether this is the same low transmittance portion of the flattening film as defined in claim 1 or a different one. For the purpose of compact prosecution, the examiner treats this to be a separate low transmittance portion associated to the edge cover.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 7-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/0258967 A1) in view of Lee (US 2023/0028691 A1) and Lin (US 2020/0227484 A1).
Regarding claim 1, Kim teaches a display device (see Title and Abstract) comprising:
a base substrate (100; Fig. 2);
a thin-film transistor layer (layer of 200; Fig. 2 shows 200 containing TFT) provided on the base substrate;
a light-emitting element layer (layer of 310 contains OLEDs, which are light-emitted diodes) provided on the thin-film transistor layer, with a plurality of first electrodes (210, see Fig. 7; alternatively, 230 is the first electrode), a plurality of light-emitting functional layers (220, see Fig. 7), and a second electrode (230; alternatively, 210 is the second electrode) that is common (230 spans across multiple Pa/Pm; see 35 USC 112(b) rejection above) being stacked sequentially (220 and 230 are stacked sequentially above 210; alternatively, 220 and 210 are stack sequentially below 230) in correspondence with a plurality of subpixels (Pm & Pa, see Figs. 1-3 and 6-8) constituting a display region (DA & NDA),
the thin-film transistor layer including a first thin-film transistor (TFTa, see Fig. 7; alternatively, TFTb or left TFT) provided for each of the plurality of subpixels, the first thin-film transistor having a first semiconductor layer (AA2; see Fig. 7 and ¶ [0124]; alternatively, AA3 in Fig 8 or A1 in Fig. 7) composed of an oxide semiconductor (¶ [0124]: IGZO, IGTZO, etc.); and
a flattening film (115 & 117 & 119) provided on the first thin-film transistor all over the display region.
However, Kim does not teach the display device further comprising of an edge cover that is common, wherein in at least a location overlapping the first thin-film transistor, the flattening film has a low-transmittance portion having a light transmittance of 80% or less at 450 nm and the display device
Lee, in the same field of invention, teaches a display device (see Tittle, Abstract) wherein in at least a location (all of 140 has this transmittance; see ¶ [0118]; Fig. 4 shows 140 overlapping DTr ) overlapping the first thin-film transistor (DTr), the flattening film (optical filter layer140 in Fig. 4 is analogous to the flattening film 115 of Kim since it is on top of TFT DTr and below light emitting element 160) has a low-transmittance portion having a light transmittance of 80% or less at 450 nm (25%, see line C in Fig. 5C and ¶ [0118] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee into the display device of Kim to set the low- light transmittance of the transmittance portion that overlaps the first thin-film transistor to be 80% or less at 450 nm of light wavelength. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for at least the purpose of using the flattening film as a filter layer (see Lee ¶ [0101] ) in order to optimize the amount of light emitted at various wavelengths depending on the color temperature of the device (¶ [0103] ) for the further purpose of improving the image displayed (¶ [0117], ¶ [0008] ).
However, Kim does not teach an edge cover that is common.
Lin, in the same field of invention, teaches a display device (¶ [0024] ) comprising an edge cover (103; Fig. 1 shows 103 covering underlying parts of the device and is found at the edges of each lighting unit LU1 ) that is common (103 is found common to all subpixels LU1; see also 35 USC 112b rejection above).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lin into the display device of Kim in view of Lee to add an edge cover that is common. The ordinary artisan would have been motivated to modify Kim in view of Lee in the manner set forth above for at least the purpose of using the edge cover as part of a shielding structure (Lin ¶ [0025]: 103 is made of light shielding materials ), so that the light of each lighting unit (LU1) will not contaminate an adjacent one, for the further purpose of enhancing the image displayed (¶ [0002] ).
Regarding claim 7, the display device according to claim 1,wherein the edge cover has the low-transmittance portion (Lin ¶ [0025]: 103 is made of light shielding materials, i.e., opaque; hence 103 has low-transmittance portion).
Regarding claim 8, the display device according to claim 1,wherein the flattening film is composed of an acrylic resin (Lee ¶ [0101] ).
Regarding claim 9, the display device according to claims 1, wherein the flattening film includes
a first flattening film (115, see Kim Fig. 7) provided in a location adjacent to the base substrate, and
a second flattening film (117&119) provided on the first flattening film, and
in each of the plurality of subpixels, the thin-film transistor layer includes a relay electrode (CM1 & CM2; alternatively, the via in layer 117 under 210 in Figs. 7-8) provided between the first flattening film and the second flattening film to relay an electrical connection between the first thin-film transistor (see ¶ [0147]: “first connection electrode CM1 may be connected to the source electrode S2 via a through hole defined in the via layer 117”; ¶ [0148]: “second connection electrode CM2 may be connected to the drain electrode SS2 via a through hole defined in the via layer 117”) and a corresponding one of the plurality of first electrodes (210 or alternatively, 230; note: 230 is the first electrode in the alternative rejection of claim 1 above).
Regarding claim 10, the display device according to claim 9, wherein the first flattening film and the second flattening film have the low-transmittance portion entirely (Kim teaches 115 and 117 to be composed of the same materials such as SiO2, SiNx, SiON, A2O3, Ta2O5, etc.; see ¶ [0131], [0134]; since Lee Fig.4 teaches applying the low-transmittance portion entirely in the layer of 140, then Kim in view of Lee teaches applying the low-transmittance portion to both the first and second flattening films ).
Regarding claim 11, the display device according to claim 10, wherein
an imaging region (SA, see Kim ¶ [0059]: “a light-receiving device may be provided together as the component 20 in the sensor area SA” ) is provided within the display region (DA; see Kim Fig. 1),
in the subpixel in the imaging region, the relay electrode (V1, see Fig. 8) is extended, so that the first thin-film transistor (TFTb; see alternative rejection for claim 1 above) corresponding to the subpixel (Pa, see Fig. 6) is provided in the subpixel around the imaging region (Fig. 6 Pa at the boundary of SA; note: ¶ [0035]: Fig. 8 is a cutaway of axis II-II’ of Fig. 6), and
the first flattening film (115), the second flattening film (117&119), and the edge cover have the low-transmittance portion (Kim in view of Lee and Lin teaches this; see claim 10 rejection above and explanation below; also, Lin ¶ [0025]: edge cover 103 is made of light shielding materials, i.e., opaque; hence 103 has low-transmittance portion) in a location not overlapping the imaging region (115 & 117 & 119 are found in SA).
As discussed in claim 1 rejection, the edge cover is taught by Lin and Lin further teaches the edge cover being used a light shielding unit (¶ [0025] ). One of ordinary skill would find it obvious to optimize the amount of light at the wavelength of 450 nm to be shielded sufficiently such that the transmittance at said wavelength is reduced. This optimization is taught by Lee (¶ [0103], ¶ [0117], ¶ [0008]) using the same thrust as explained in claim 1 rejection above.
Regarding claim 12, the display device according to claim 1, comprising a sealing film (320 & 330; see Kim Fig. 2) provided so as to cover the light-emitting element layer.
Regarding claim 13, the display device according to claim 1,wherein each of the plurality of light-emitting functional layers is an organic electroluminescence layer (Kim ¶ [0142]: 220 is an organic light-emitting diode made of fluorescent or phosphorescent that emits light when holes/electrons are present ).
Claims 2-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/0258967 A1) in view of Lee (US 2023/0028691 A1) and Lin (US 2020/0227484 A1) as applied to claim 1 above and further in view of Saitoh (US 2021/0028314 A1).
Regarding claim 2, Kim et al. teach the display device according to claim 1, wherein
the first thin-film transistor includes the first semiconductor layer provided on a first interlayer insulating film (111, Kim Fig. 7; ¶ [0121]: made of oxide or nitride ), the first semiconductor layer having a first region (left AA2 connected to SS2) and a second region (right AA2 connected to DD2) defined so as to be spaced from each other (both regions are spaced apart from each other along the horizontal axis), and a first middle region (region in between left AA2 and right AA2) defined between the first region and the second region,
a first gate insulating film (112) provided on the first semiconductor layer,
a first gate electrode (GG2) provided on the first gate insulating film so as to overlap the first middle region (GG2 overlaps the region between left AA2 and right AA2),
a second interlayer insulating film (113) provided so as to cover the first gate electrode, and
a first terminal electrode (SS2) and a second terminal electrode (DD2) provided on the second interlayer insulating film (SS2 and DD2 are above 113) so as to be spaced from each other (SS2 and DD2 are spaced apart along the horizontal axis), and electrically connected to the first region (left AA2) and the second region (right AA2), respectively.
However, Kim et al. do not teach the first thin-film transistor wherein first region is a first conductor region, the second region is a second conductor region, and the first middle region is a first channel region.
Saitoh, in the same field of invention, teaches a first thin-film transistor (10) wherein first region (11A) is a first conductor region (¶ [0114] ), the second region (11B) is a second conductor region (¶ [0114] ), and the first middle region (11C) is a first channel region (¶ [0114] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Saitoh into the device of Kim et al. to modify the first thin-film transistor such that the first region is a first conductor region, the second region is a second conductor region, and the first middle region is a first channel region. The ordinary artisan would have been motivated to modify Kim et al. in the manner set forth above for at least the purpose of improving desired attributes of the thin-film transistor (Saitoh ¶ [0114]: gentle rise of a drive voltage ) that is suitable to a type of display device (¶ [0114]: current driving type; see also ¶ [0005]-[0010] ).
Regarding claim 3, the display device according to claim 2, wherein the thin-film transistor layer includes, in addition to the first thin-film transistor, a second thin-film transistor (left TFT in Kim Fig. 7) provided for each of the plurality of subpixels, the second thin-film transistor having a second semiconductor layer (A1) composed of polysilicon (Kim ¶ [0124]: “A1… may include amorphous silicon or polysilicon”).
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/0258967 A1) in view of Lee (US 2023/0028691 A1), Lin (US 2020/0227484 A1) and Saitoh (US 2021/0028314 A1) as applied to claim 2 above, and further in view of Seo (US 2021/0296367 A1).
Regarding claim 4, Kim et al. teach the display device according to claim 3, wherein the second thin-film transistor includes
the second semiconductor layer having a third conductor region (left A1, see Kim Fig.7; Kim in view of Saitoh teaches this to be a third conductor region) and a fourth conductor region (right A1; Kim in view of Saitoh teaches this to be a fourth conductor region) defined so as to be spaced from each other (spaced apart along the horizontal axis), and a second channel region (space between left A1 and right A1; Kim in view of Saitoh teaches this to be a second channel region) defined between the third conductor region and the fourth conductor region,
a second gate electrode (G1) provided on the second gate insulating film so as to overlap the second channel region (G1 overlaps the region between left A1 and right A1),
a third terminal electrode (S1) and a fourth terminal electrode (D1) provided on the second interlayer insulating film (S1 and D1 are on top of 113) so as to be spaced from each other (spaced along the horizontal axis), and electrically connected to the third conductor region (left A1) and the fourth conductor region (left A2), respectively.
However Kim et al. do not each the display device comprising a second gate insulating film provided on the second semiconductor layer, and the first interlayer insulating film and the second interlayer insulating film sequentially provided so as to cover the second gate electrode.
Seo, in the same field of invention, teaches a display device comprising
a second gate insulating film (111, see Fig. 4) provided on the second semiconductor layer (105), and
the first interlayer insulating film (113) and the second interlayer insulating film (115) sequentially provided (Fig. 4 shows 115 directly on top of 113) so as to cover the second gate electrode (121).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Seo into the device of Kim et al. to add a second gate insulating film on the second semiconductor layer and to modify the structure of the device such that the first interlayer insulating film and the second interlayer insulating film are sequentially provided and cover the second gate electrode. The ordinary artisan would have been motivated to modify Kim et al. in the manner set forth above for at least the purpose of using the second gate insulating film to set the second thin-film transistor at a vertical position lower than the first thin-film transistor to allow the first interlayer insulating layer and second interlayer insulating layer to be comprised of a plurality of layers (113a-b, 115a-c; see Seo Fig. 4) for the purpose of optimizing the hydrogen concentration of said layers (see ¶ [0115], ¶ [0127], ¶ [0130]-[0132] ), for the further purpose of optimizing the threshold voltage of the thin-film transistors (Figs. 17-18; ¶ [0176]-[0178] ) .
Regarding claim 6, the display device according to claim 4, wherein the flattening film (115, Kim Fig. 7) has the low-transmittance portion in a location (Lee Fig. 4 teaches all of 140 has this transmittance; see ¶ [0118]) overlapping the second gate electrode, the third terminal electrode, and the fourth terminal electrode (Kim Fig. 7 shows 115 on top of and overlapping S1, G1 and D1).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/0258967 A1) in view of Lee (US 2023/0028691 A1), Lin (US 2020/0227484 A1) and Saitoh (US 2021/0028314 A1) as applied to claim 2 above, and further in view of Fukai (US 2021/0150994 A1).
Regarding claim 5, Kim et al. teach the display device according to claim 2, but does not teach: wherein the first thin-film transistor includes a third gate electrode provided on the first semiconductor layer adjacent to the base substrate, with the first interlayer insulating film interposed between the third gate electrode and the first semiconductor layer so as to overlap the first semiconductor layer.
Fukai, in the same field of invention, teaches a display device wherein the first thin-film transistor includes a third gate electrode (517; Fig. 16 and ¶ [0227] ) provided on the first semiconductor layer (512) adjacent to the base substrate (4001), with the first interlayer insulating film (4103) interposed between the third gate electrode and the first semiconductor layer so as to overlap the first semiconductor layer (Fig. 16 shows 4103 in between 517 and 512 and overlapping 512).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Fukai into the display device of Kim et al. to add a third gate electrode to the base substrate, wherein the first interlayer insulating film is in between the third gate electrode and the first semiconductor layer. The ordinary artisan would have been motivated to modify Kim et al. in the manner set forth above for at least the purpose of using the third gate electrode as a back gate of the first thin-film transistor (Fukai ¶ [0228] ) for the further purpose of improving the performance of the first thin-film transistor (¶ [0229] ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
1 Plain meaning of “common” is “belong to or shared by two or more entities.”
Prosecution Insights