DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election, without traverse, of Group I: claims 1-11 in the “Response to Election / Restriction Filed -06/30/2026”, is acknowledged along with cancellation of claims 12, 15 and 24.
This office action considers claims 1-11, 13-14, 16-23 pending for prosecution of which claims 13-14, 16-23 are withdrawn and claims 1-11 are presented for examination on merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (10; Fig 1; [0048]) = (element 10; Figure No. 1; Paragraph No. [0049]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation may not be preceded by the inventor tag, wherein the other reference citation will carry inventor tag. These conventions are used throughout this document.
Claims 1-5 and 7 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Liu; Tzuan-Horng et al. (US 20120305916 A1) hereinafter Liu;
Regarding claim 1, Liu teaches a chip testing structure ([0047]: interposer and die attached to it, including test structures for testing the reliability of processing for structures corresponding to the test structures), comprising (see the entire document, figs 2F,1 along with relevant figures 2A-2E, 3-39, paragraphs [0048-0138], specifically as cited below):
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Liu Figures 2F Figure 1
an interposer (interposer 10; Figs 1, 2F; first cited in [0048]), a plurality of chips (58; Figs 2D; [0056]) on the interposer (10), and a plurality of test points (210, labelled as probe pads i.e. test points; Figs 9-10; [0077-0078]: the probe pad 210 is formed, contemporaneously with bump bond pads, such as bump bond pads 54 in FIG. 2C. The probe pad 210 is formed in the corner and is electrically coupled through an interconnect structure (not shown in FIG. 9) and a line 202 to the inner seal ring pattern 136 ) on the interposer (10);
wherein the plurality of the test points (210) are connected in series (Figure 10, depicts the probe pads 210 (i.e. Test sites) are connected in series), an electrical connecting wire of the plurality of the test points (210) is provided in an interposer wiring layer (IMD 152) of the interposer (10), and an electrical connecting wire of adjacent test potentials comprises a plurality of sub-connecting wires (214, 216, 218, 220), different sub-connecting wires are positioned at different heights (depicted in Fig 10) of the interposer wiring layer (IMD 152), and the plurality of the sub-connecting wires are connected sequentially based on a height of the interposer wiring layer (IMD 152); and
wherein when test potentials of the plurality of the test points (210 ) indicate an open circuit connection, the interposer (10) is indicated to be fragmented or have a crack ([0080]: by applying a signal at one probe pad 210, it can be determined whether the segment under test 212 has a void or discontinuity (i.e., indicating fragmentation or the presence of a crack in the adapter when the test potentials at the multiple test sites appear as open connections) in the metallization of the segment by sensing a signal at another probe pad 210 at an opposite end of the segment under test 212).
Regarding claim 2, Liu as applied to the chip testing structure of claim 1, further teaches, wherein sub-connecting wires (IMD) of the plurality of the test points (210 labelled as 408 in Fig 24; [0103]) are displayed as a serpentine shape (depicted in Fig 24; [0103]:labelled as stair-stepped ) on a cross-section of the interposer (10) according to a wiring distribution sequence of the interposer wiring layer (IMD).
Regarding claim 3, Liu as applied to the chip testing structure of claim 1, further teaches, wherein the plurality of the test points (probe pads 230,232,234; Fig 11; [0081]) at least comprise a first test point (230), a second test point *232), and a third test point ((234));
a position interval between the first test point (230) and the second test point (232) on the interposer is a first value, a position interval between the first test point (230) and the third test point (234) on the interposer is a second value, and a position interval between the second test point (232) and the third test point (234) on the interposer is a third value (depicted in Figs 12A, 12B,12C; [0082]) ;
the second value and the third value are determined based on the first value, and the second value is equal to the third value; and
in response to the first test point (230) and the second test point (232) being in the open circuit connection, the third test point (234) is determined as the first test point or the second test point (see [0084-0086]).
Regarding claim 4, Liu as applied to the chip testing structure of claim 3, further teaches, wherein in a distribution direction of the plurality of the test points (probe pads 230,232,234; Fig 11, 12A to 12C; [0081-0086]) around the interposer, the first test point (230) and the second test point (22) are respectively positioned at a start point and an end point, and the first value is a maximum value of position intervals on the interposer (10)
Regarding claim 5, Liu as applied to the chip testing structure of claim 1, further teaches, wherein the interposer wiring layer (of IMD 152) comprises a first intermediate layer (270; Fig 1C) and a second intermediate layer (252; Fig 12B) bonded below the first intermediate layer (270), and an electrical connecting wire of the first intermediate layer is in communication with an electrical connecting wire of the second intermediate layer; and a bonding quality of the first intermediate layer and the second intermediate layer is determined according to the test potentials of the plurality of the test points (230,234,234).
Regarding claim 7, Liu as applied to the chip testing structure of claim 1, further teaches, wherein a plurality of through-vias electrodes (TSV 42; Fig 2A; [0050]; detailed as 92 in Fig 4; [0066]) electrically connected with the test points (210; Fig 10) are provided on the interposer (10), and a plurality of interconnection structures through the chips (12 or 58 in Fig 2D) are provided on the chips ;
the chips (12/58) are bonded to the interposer (10), wherein a bottom of the interconnection structures is electrically connected with the through-vias electrodes (TSV 42), and a top of the interconnection structures is provided with interconnection solder balls (56; first cited in Fig 2C; [0056]);
when a voltage is applied to the test points (210) and the interconnecting solder balls electrically connected to the test points (, and test potentials of the interconnecting solder balls (56) electrically connected with the test points (210) indicate a preset potential, the interconnecting solder balls are indicated to be electrically connected with the interconnection structures (construed from [0080]: by applying a signal at one probe pad 210, it can be determined whether the segment under test 212 has a void or discontinuity (i.e., indicating fragmentation or the presence of a crack in the adapter when the test potentials at the multiple test sites appear as open connections) in the metallization of the segment by sensing a signal at another probe pad 210 at an opposite end of the segment under test 212).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Liu; Tzuan-Horng et al. (US 20120305916 A1) hereinafter Liu;.
Regarding claim 6, Liu as applied to the chip testing structure of claim 1, further teaches, wherein a plurality of sub- connecting wires (of IMD152) of corresponding test points (408) constitute a comb-shaped short-circuit measurement structure (labelled as ladder; Fig 25; [0104]), and a comb-shaped short-circuit measurement structure between adjacent test points (408) is in open-circuit connection; wherein when the test potentials of the plurality of the test points (408) indicate a short-circuit connection, the plurality of the test points (408) are indicated to be short-connected at front of the interposer; or a serpentine open-circuit measurement structure (Fig 24) with stacked through vias is correspondingly provided between adjacent test points; wherein when the test potentials of the plurality of the test points indicate the open circuit connection, the plurality of the test points (408) are indicated to be open-connected at the front of the interposer.
Moreover, both comb short circuit measurement structures and serpentine open circuit measurement structures are circuit measurement structures commonly used in the art and belong to common general knowledge. Accordingly, the subject matter claimed in this claim (s) is devoid of outstanding features and significant advancements, and thus is not inventive.
Regarding claim 8, Liu as applied to the chip testing structure of claim 7, further teaches, wherein solder balls (56; first cited in Fig 2C; [0056]) at two ends of a chip circuit structure are served as circuit testing solder balls, a chip circuit testing structure is provided between the circuit testing solder balls, the chip circuit testing structure is configured to electrically connect the circuit testing solder balls, and when test potentials of test points electrically connected with the circuit testing solder balls indicate the open circuit connection, the chip circuit structure is indicated to be damaged (i.e., obvious from [0080]: by applying a signal at one probe pad 210, it can be determined whether the segment under test 212 has a void or discontinuity (i.e., indicating fragmentation or the presence of a crack in the adapter when the test potentials at the multiple test sites appear as open connections) in the metallization of the segment by sensing a signal at another probe pad 210 at an opposite end of the segment under test 212).
Regarding claim 9, Liu as applied to the chip testing structure of claim 7, further teaches, wherein interposer solder balls (56; first cited in Fig 2C; [0056]) are provided on through-vias electrodes (TSV 42; Fig 2A; [0050]; detailed as 92 in Fig 4; [0066]) at a side of the interposer (10) away from the chips (12/58) , an interposer solder ball testing structure is provided on solder balls of the through-vias electrodes that are provided with the interposer solder balls, the interposer solder balls are configured to be short- connected with the interposer solder ball testing structure, and
when a test voltage is applied to the interposer solder balls, and test potentials between the interposer solder balls indicate that the interposer solder balls are short-connected, the interposer solder balls are indicated to be electrically connected with the through-vias electrodes (i.e., obvious from [0080]: by applying a signal at one probe pad 210, it can be determined whether the segment under test 212 has a void or discontinuity (i.e., obvious from [0080]: by applying a signal at one probe pad 210, it can be determined whether the segment under test 212 has a void or discontinuity (i.e., indicating fragmentation or the presence of a crack in the adapter when the test potentials at the multiple test sites appear as open connections) in the metallization of the segment by sensing a signal at another probe pad 210 at an opposite end of the segment under test 212).
Regarding claim 10, Liu as applied to the chip testing structure of claim 9, further teaches, further comprising a substrate ({84,82}; Fig 3D; [0064]),
wherein an interposer structure (10) and bottom solder balls (56; first cited in Fig 2C; [0056]) at bottom of the interposer structure are provided in the substrate ({84,82}), and the interposer (10) is connected to the bottom solder balls (56) based on the interposer solder balls and the interposer structure of the substrate; and
when a test voltage is applied on the bottom solder balls (56) to through-vias electrodes (TSV 42; Fig 2A; [0050]; detailed as 92 in Fig 4; [0066]) that are short-connected, and test potentials between the bottom solder balls indicate that the bottom solder balls (56) are short-circuit, the bottom solder balls (56) are indicated to be electrically connected with the interposer (i.e., (i.e., obvious from [0080]: by applying a signal at one probe pad 210, it can be determined whether the segment under test 212 has a void or discontinuity (i.e., indicating fragmentation or the presence of a crack in the adapter when the test potentials at the multiple test sites appear as open connections) in the metallization of the segment by sensing a signal at another probe pad 210 at an opposite end of the segment under test 212)).
Regarding claim 11, Liu as applied to the chip testing structure of claim 10, further teaches, wherein
when a test voltage is applied on the bottom solder balls (56; first cited in Fig 2C; [0056]) to interconnecting solder balls that are short- connected, and the test potentials between the bottom solder balls indicate that the bottom solder balls are short-circuit, the bottom solder balls are indicated to be electrically connected with the chips; or wherein when a test voltage is applied on the bottom solder balls to a short-connected circuit that is mixed-connected with the interconnecting solder balls and through-vias electrodes (TSV 42; Fig 2A; [0050]; detailed as 92 in Fig 4; [0066]), and the test potentials between the bottom solder balls indicate that the bottom solder balls are short-circuit, the bottom solder balls are indicated to be electrically connected with the chips (12/58) and the interposer (10) (i.e., indicating fragmentation or the presence of a crack in the adapter when the test potentials at the multiple test sites appear as open connections) in the metallization of the segment by sensing a signal at another probe pad 210 at an opposite end of the segment under test 212).
Conclusion
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
July 23, 2026
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