Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application(s) filed in Japan on 11/05/2021 and 11/19/2021.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 08/02/2024 and 07/17/2026 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0311245 A1; Yamazaki et al.; 10/2015; (“Yamazaki”) in view of US 2013/0141157 A1; Takemura, Yasuhiko; 06/2013; (“Takemura”).
Regarding Claim 1. Yamazaki discloses A semiconductor device (Figure 1A) comprising:
a first layer (#1100, Figure 1A, first layer); and
a second layer (#1300, Figure 1A, third layer) over the first layer (Figure 1A, #1300 is over #1100),
wherein the first layer (#1100) comprises a p-channel first transistor (#51, Figure 1A, [0126], p-channel transistor) comprising silicon in a first channel formation region ([0126], #51 has its active region or channel in the silicon substrate #40),
wherein the second layer comprises an n-channel second transistor (#53, Figure 1A, [0126], n-channel transistor) comprising a metal oxide in a second channel formation region ([0126], #53 has an oxide semiconductor as its channel, [0025] of the instant application states “Metal oxides are classified into . . . an oxide semiconductor (also simply referred to as an OS), and the like”),
wherein the first transistor and the second transistor form a CMOS circuit (Figure 1C, [0125], #51 and #53 form a CMOS inverter).
Yamazaki does not explicitly disclose that a channel length of the first transistor is longer than a channel length of the second transistor.
However, Takemura teaches in [0012] that “oxide semiconductor has a field-effect mobility which is less than or equal to 1/10 of that of silicon” and further teaches in [0184] that “when an inverter is formed using an n-channel transistor and a p-channel transistor, their channel length and channel width are preferably determined in consideration of the mobility so that the transistors have substantially symmetrical on-state characteristics”. The channel length of the transistors are therefore result-effective variables.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to vary, through routine optimization, the channel lengths of the first and second transistors as they have been identified as result effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the channel length of the first (silicon) transistor being longer than the channel length of the second (oxide semiconductor) transistor, in order to achieve the desired balance in mobilities between the two transistors for the operation of the inverter as taught by Takemura. (see MPEP 2144.05.II) Furthermore, the applicant has not presented persuasive evidence that the claimed relative channel lengths are for a purpose that is critical to the overall claimed invention (i.e. that the invention would be inoperable without the specified claimed relative channel lengths).
Regarding Claim 2. Yamazaki discloses A semiconductor device (Figure 1A) comprising:
a first layer (#1100, Figure 1A, first layer); and
a second layer (#1300, Figure 1A, third layer) over the first layer (Figure 1A, #1300 is over #1100),
wherein the first layer (#1100) comprises a p-channel first transistor (#51, Figure 1A, [0126], p-channel transistor) comprising silicon in a first channel formation region ([0126], #51 has its active region or channel in the silicon substrate #40),
wherein the second layer comprises an n-channel second transistor (#53, Figure 1A, [0126], n-channel transistor) comprising a metal oxide in a second channel formation region ([0126], #53 has an oxide semiconductor as its channel, [0025] of the instant application states “Metal oxides are classified into . . . an oxide semiconductor (also simply referred to as an OS), and the like”),
wherein the first transistor and the second transistor form a CMOS circuit (Figure 1C, [0125], #51 and #53 form a CMOS inverter).
Yamazaki does not explicitly disclose that a channel length of the first transistor is longer than a channel length of the second transistor, wherein the channel length of the first transistor is greater than or equal to 15 nm, and wherein the channel length of the second transistor is less than 15 nm.
However, Takemura teaches in [0012] that “oxide semiconductor has a field-effect mobility which is less than or equal to 1/10 of that of silicon” and further teaches in [0184] that “when an inverter is formed using an n-channel transistor and a p-channel transistor, their channel length and channel width are preferably determined in consideration of the mobility so that the transistors have substantially symmetrical on-state characteristics”. The channel length of the transistors are therefore result-effective variables.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to vary, through routine optimization, the channel lengths of the first and second transistors as they have been identified as result effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the channel length of the first (silicon) transistor, being greater than 15 nm, being longer than the channel length of the second (oxide semiconductor) transistor, being less than 15 nm, in order to achieve the desired balance in mobilities between the two transistors for the operation of the inverter as taught by Takemura. (see MPEP 2144.05.II) Furthermore, the applicant has not presented persuasive evidence that the claimed relative channel lengths are for a purpose that is critical to the overall claimed invention (i.e. that the invention would be inoperable without the specified claimed relative channel lengths).
Regarding Claim 3. Yamazaki discloses A semiconductor device (Figure 1A) comprising:
a first layer (#1100, Figure 1A, first layer); and
a second layer (#1300, Figure 1A, third layer) over the first layer (Figure 1A, #1300 is over #1100),
wherein the first layer (#1100) comprises a p-channel first transistor (#51, Figure 1A, [0126], p-channel transistor) comprising silicon in a first channel formation region ([0126], #51 has its active region or channel in the silicon substrate #40),
wherein the second layer comprises an n-channel second transistor (#53, Figure 1A, [0126], n-channel transistor) comprising a metal oxide in a second channel formation region ([0126], #53 has an oxide semiconductor as its channel, [0025] of the instant application states “Metal oxides are classified into . . . an oxide semiconductor (also simply referred to as an OS), and the like”),
wherein the first transistor and the second transistor form a CMOS circuit (Figure 1C, [0125], #51 and #53 form a CMOS inverter).
Yamazaki does not explicitly disclose that a channel length of the first transistor is longer than a channel length of the second transistor, wherein the channel length of the first transistor is greater than or equal to 15 nm and less than or equal to 40 nm, and wherein the channel length of the second transistor is greater than or equal to 3 nm and less than 15 nm.
However, Takemura teaches in [0012] that “oxide semiconductor has a field-effect mobility which is less than or equal to 1/10 of that of silicon” and further teaches in [0184] that “when an inverter is formed using an n-channel transistor and a p-channel transistor, their channel length and channel width are preferably determined in consideration of the mobility so that the transistors have substantially symmetrical on-state characteristics”. The channel length of the transistors are therefore result-effective variables.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to vary, through routine optimization, the channel lengths of the first and second transistors as they have been identified as result effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the channel length of the first (silicon) transistor, being between 15 nm and 40 nm, inclusive, being longer than the channel length of the second (oxide semiconductor) transistor, being less than 15 nm and greater than or equal to 3 nm, in order to achieve the desired balance in mobilities between the two transistors for the operation of the inverter as taught by Takemura. (see MPEP 2144.05.II) Furthermore, the applicant has not presented persuasive evidence that the claimed relative channel lengths are for a purpose that is critical to the overall claimed invention (i.e. that the invention would be inoperable without the specified claimed relative channel lengths).
Regarding Claim 4. Yamazaki in view of Takemura disclose The semiconductor device according to claim 1,
wherein the first layer comprises a single crystal silicon substrate (Yamazaki, [0173] and [0359], the device substrate may be a single crystal silicon substrate), and
wherein the first transistor comprises the first channel formation region in the single crystal silicon substrate (Yamazaki, Figure 1A, #51 has its channel formation region in the substrate which is single crystal silicon).
Regarding Claim 5. Yamazaki in view of Takemura disclose The semiconductor device according to any one of claim 1,
wherein the second layer (Yamazaki, #1300) comprises a memory circuit (Yamazaki, #91, Figures 1A and 1B, #1300 includes a portion of #91 which is interpreted at least partially as a memory circuit for its inclusion of charge storage portion #FD which may be interpreted as a form of memory by storing a charge value).
Regarding Claim 6. Yamazaki in view of Takemura disclose The semiconductor device according to claim 5, the memory circuit (Yamazaki, #91, Figure 1B) further comprising:
a third transistor (Yamazaki, #52, Figure 1B, transistor);
a fourth transistor (Yamazaki, #54, Figure 1B, transistor); and
a capacitor (Yamazaki, [0181], a storage capacitor may be provided and connected to the charge storage portion #FD),
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor (Yamazaki, Figure 1B, a source/drain of #52 is electrically connected to a gate of #54), and
wherein the gate of the fourth transistor is electrically connected to one electrode of the capacitor (Yamazaki, Figure 1B, [0181], the gate of #54 is electrically connected to #FD which is electrically connected to at least one plate of the storage capacitor).
Regarding Claim 7. Yamazaki in view of Takemura disclose The semiconductor device according to claim 6,
wherein the third transistor (Yamazaki, #52) and the fourth transistor (Yamazaki, #54) each comprise the metal oxide of the second channel formation region in a channel formation region ([0126], “transistors 52 to 55 each including the oxide semiconductor layer as the active layer”, i.e. #52 and #54 both comprise the same oxide semiconductor as #53 in their channel formation region).
Regarding Claim 8. Yamazaki in view of Takemura disclose An electronic device comprising:
the semiconductor device according to claim 1; and a display portion (Yamazaki, [0488]-[0494], the semiconductor device may be utilized in an electronic display device which necessarily includes a display).
Regarding Claim 9. Yamazaki in view of Takemura disclose The semiconductor device according to claim 2,
wherein the first layer comprises a single crystal silicon substrate (Yamazaki, [0173] and [0359], the device substrate may be a single crystal silicon substrate), and
wherein the first transistor comprises the first channel formation region in the single crystal silicon substrate (Yamazaki, Figure 1A, #51 has its channel formation region in the substrate which is single crystal silicon).
Regarding Claim 10. Yamazaki in view of Takemura disclose The semiconductor device according to any one of claim 2,
wherein the second layer (Yamazaki, #1300) comprises a memory circuit (Yamazaki, #91, Figures 1A and 1B, #1300 includes a portion of #91 which is interpreted at least partially as a memory circuit for its inclusion of charge storage portion #FD which may be interpreted as a form of memory by storing a charge value).
Regarding Claim 11. Yamazaki in view of Takemura disclose An electronic device comprising:
the semiconductor device according to claim 2; and a display portion (Yamazaki, [0488]-[0494], the semiconductor device may be utilized in an electronic display device which necessarily includes a display).
Regarding Claim 12. Yamazaki in view of Takemura disclose The semiconductor device according to claim 3,
wherein the first layer comprises a single crystal silicon substrate (Yamazaki, [0173] and [0359], the device substrate may be a single crystal silicon substrate), and
wherein the first transistor comprises the first channel formation region in the single crystal silicon substrate (Yamazaki, Figure 1A, #51 has its channel formation region in the substrate which is single crystal silicon).
Regarding Claim 13. Yamazaki in view of Takemura disclose The semiconductor device according to any one of claim 3,
wherein the second layer (Yamazaki, #1300) comprises a memory circuit (Yamazaki, #91, Figures 1A and 1B, #1300 includes a portion of #91 which is interpreted at least partially as a memory circuit for its inclusion of charge storage portion #FD which may be interpreted as a form of memory by storing a charge value).
Regarding Claim 14. Yamazaki in view of Takemura disclose An electronic device comprising:
the semiconductor device according to claim 3; and a display portion (Yamazaki, [0488]-[0494], the semiconductor device may be utilized in an electronic display device which necessarily includes a display).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2017/0018577 A1; Matsuda, Shinpei; 01/2017 – Figures 36A and 36B disclose a vertically integrated CMOS inverter comprising a silicon P-FET and an oxide semiconductor N-FET in a layer above the P-FET wherein the mobility of the transistors is closest together in the given channel length ranges (see Figure 4) for the respective transistors.
US 2015/0348997 A1; Sasagawa et al.; 12/2015 – Figures 1A and 1B disclose a vertically integrated CMOS inverter comprising a silicon P-FET and an oxide semiconductor N-FET in a layer above the P-FET.
US 2015/0372009 A1; Yamazaki, Shunpei; 12/2015 – Figures 14A and 15 disclose a vertically integrated CMOS inverter comprising a silicon P-FET and an oxide semiconductor N-FET in a layer above the P-FET.
US 10,522,693 B2; Kurokawa, Yoshiyuki; 12/2019 – Figure 5 discloses a vertically integrated CMOS inverter comprising a silicon P-FET and an oxide semiconductor N-FET in a layer above the P-FET wherein the device is part of a larger memory/display device.
US 12,598,806 B2; Jang et al.; 04/2026 – Figure 2A discloses a CMOS inverter comprising a silicon P-FET and an oxide semiconductor N-FET wherein the channel lengths of the transistors are different (column 3, lines 38-41).
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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