CTNF 18/707,987 CTNF 89876 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Koezuka et al. (U.S. 2021/0167212 A1, hereinafter refer to Koezuka) in view of Gosavi et al. (U.S. 2020/0212193, hereinafter refer to Gosavi) . Regarding Claim 1: Koezuka discloses a memory element (see Koezuka, Fig.2 as shown below and ¶ [0001]) comprising PNG media_image1.png 283 708 media_image1.png Greyscale PNG media_image2.png 228 536 media_image2.png Greyscale a first electrode ( 106 ) that comprises a region overlapping with a semiconductor layer ( 108 ) with a first insulating layer ( 103 ) therebetween and a second electrode ( 112 ) that comprises a region overlapping with the semiconductor layer ( 108 ) with a second insulating layer ( 110 ) therebetween (see Koezuka, Fig.2 as shown above), wherein the first electrode ( 106 ) and the second electrode ( 112 ) comprise a region where they overlap with each other with the first insulating layer ( 103 ), the semiconductor layer ( 108 ), and the second insulating layer ( 110 ) therebetween (see Koezuka, Fig.2 as shown above), wherein the semiconductor layer ( 108 ) comprises an oxide semiconductor (see Koezuka, Fig.2 as shown above and ¶ [0100]- ¶ [0115]). Koezuka is silent upon explicitly disclosing wherein the first insulating layer has anti-ferroelectricity. For support see Gosavi, which teaches wherein the first insulating layer ( 106 ) has anti-ferroelectricity (see Gosavi, Fig.4 as shown below, abstract, ¶ [0030], and ¶ [0057]- ¶ [0066]). PNG media_image3.png 378 619 media_image3.png Greyscale Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Koezuka and Gosavi to enable the Koezuka’s first insulating layer to have anti-ferroelectricity properties as taught by Gosavi in order to increases the strain/stress generated in the gate of the transistors. Regarding Claim 2: Koezuka discloses a memory element (see Koezuka, Figs.2 and 4 as shown above and ¶ [0001]) comprising a first electrode ( 106 ) that comprises a region overlapping with a first region of a semiconductor layer ( 108 ) with a first insulating layer ( 103 ) therebetween, a second electrode ( 112 ) that comprises a region overlapping with the first region with a second insulating layer ( 110 ) therebetween, a third electrode ( 120a ) electrically connected to a second region of the semiconductor layer ( 108 ), and a fourth electrode ( 120b ) electrically connected to a third region of the semiconductor layer ( 108 ) (see Koezuka, Figs.2 and 4 as shown above), wherein the first electrode ( 106 ) and the second electrode ( 112 ) comprise a region where they overlap with each other with the first insulating layer ( 103 ), the first region, and the second insulating layer ( 110 ) therebetween (see Koezuka, Fig.2 as shown above), wherein the semiconductor layer ( 108 ) comprises an oxide semiconductor (see Koezuka, Fig.2 as shown above and ¶ [0100]- ¶ [0115]). Koezuka is silent upon explicitly disclosing wherein the first insulating layer has anti-ferroelectricity. For support see Gosavi, which teaches wherein the first insulating layer ( 106 ) has anti-ferroelectricity (see Gosavi, Fig.4 as shown above, abstract, ¶ [0030], and ¶ [0057]- ¶ [0066]). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Koezuka and Gosavi to enable the Koezuka’s first insulating layer to have anti-ferroelectricity properties as taught by Gosavi in order to increases the strain/stress generated in the gate of the transistors. Regarding Claim 3: Koezuka as modified teaches a memory element as set forth in claim 1 as above. The combination of Koezuka and Gosavi further teaches wherein the semiconductor layer ( 108 ) comprises at least one of indium and zinc (see Koezuka, Fig.2 as shown above and ¶ [0100]- ¶ [0115]). Regarding Claim 4: Koezuka as modified teaches a memory element as set forth in claim 1 as above. The combination of Koezuka and Gosavi further teaches wherein the first insulating layer ( 106 ) comprises hafnium (see Gosavi, Fig.4 as shown above, abstract, ¶ [0030], and ¶ [0057]- ¶ [0066]). Regarding Claim 5: Koezuka as modified teaches a memory element as set forth in claim 4 as above. The combination of Koezuka and Gosavi further teaches wherein the first insulating layer ( 106 ) comprises zirconium (see Gosavi, Fig.4 as shown above, abstract, ¶ [0030], and ¶ [0057]- ¶ [0066]). Regarding Claim 6: Koezuka as modified teaches a memory element as set forth in claim 1 as above. The combination of Koezuka and Gosavi further teaches wherein the semiconductor layer ( 108 ) comprises at least one of hydrogen, nitrogen, phosphorus, fluorine, chlorine, and a noble gas (see Koezuka, Fig.2 as shown above and ¶ [0165]). Regarding Claim 7: Koezuka as modified teaches a memory element as set forth in claim 1 as above. The combination of Koezuka and Gosavi further teaches wherein the memory element is configured to retain multilevel data (see Koezuka, Fig.2 as shown above). Regarding Claim 9: Koezuka as modified teaches a memory element as set forth in claim 2 as above. The combination of Koezuka and Gosavi further teaches wherein the semiconductor layer ( 108 ) comprises at least one of indium and zinc (see Koezuka, Fig.2 as shown above and ¶ [0100]- ¶ [0115]). Regarding Claim 10: Koezuka as modified teaches a memory element as set forth in claim 2 as above. The combination of Koezuka and Gosavi further teaches wherein the first insulating layer ( 106 ) comprises hafnium (see Gosavi, Fig.4 as shown above, abstract, ¶ [0030], and ¶ [0057]- ¶ [0066]). Regarding Claim 11: Koezuka as modified teaches a memory element as set forth in claim 10 as above. The combination of Koezuka and Gosavi further teaches wherein the first insulating layer ( 106 ) comprises zirconium (see Gosavi, Fig.4 as shown above, abstract, ¶ [0030], and ¶ [0057]- ¶ [0066]). Regarding Claim 12: Koezuka as modified teaches a memory element as set forth in claim 2 as above. The combination of Koezuka and Gosavi further teaches wherein the semiconductor layer ( 108 ) comprises at least one of hydrogen, nitrogen, phosphorus, fluorine, chlorine, and a noble gas (see Koezuka, Fig.2 as shown above and ¶ [0165]). Regarding Claim 13: Koezuka as modified teaches a memory element as set forth in claim 2 as above. The combination of Koezuka and Gosavi further teaches wherein the memory element is configured to retain multilevel data (see Koezuka, Fig.2 as shown above). Regarding Claim 14: Koezuka as modified teaches a memory element as set forth in claim 2 as above. The combination of Koezuka and Gosavi further teaches a memory device comprising a memory array that comprises a plurality of the memory elements described in claim 2 and a driver circuit ( 704 ) (see Koezuka, Fig.2 as shown above, Fig.13, and ¶ [0344]- ¶ [0346]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BITEW A DINKE/Primary Examiner, Art Unit 2812 Application/Control Number: 18/707,987 Page 2 Art Unit: 2812 Application/Control Number: 18/707,987 Page 3 Art Unit: 2812 Application/Control Number: 18/707,987 Page 4 Art Unit: 2812 Application/Control Number: 18/707,987 Page 5 Art Unit: 2812 Application/Control Number: 18/707,987 Page 6 Art Unit: 2812 Application/Control Number: 18/707,987 Page 7 Art Unit: 2812 Application/Control Number: 18/707,987 Page 8 Art Unit: 2812 Application/Control Number: 18/707,987 Page 9 Art Unit: 2812
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