DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Claims 1, 11 and 12 recite the limitation wherein “a dummy gate astride the channel stack”. If the applicant used the term “astride” to mean that the dummy gate is conformally formed on either side of the channel stack, then, this step must be shown in the drawings.
Claim 3 recites the limitation wherein, “ forming a first film covering a surface of the substrate and the channel stack; and etching the first film according to a pattern of the channel stack to form the dummy gate”. These steps are not shown in any drawings. No drawings show how the device would look like before the etching step.
Claim 3 further recites “a first direction” and “a second direction”. These features are also not shown in any drawings.
Claim 4 recites the limitation wherein, “forming a second film which covers the dummy gate, the channel stack, and the substrate”, and “etching the second film to form the first spacer covering side surfaces and a top surface of the dummy gate”. These steps are not shown in any drawings. No drawings show how the device would look like before the etching step.
Claim 4 further recites “the first direction”. This feature is also not shown in any drawings.
Claim 6 recites the limitation wherein forming “a third film of which a thickness is more than or equal to the depth of the recesses; and etching the third film”. These steps are not shown in any drawings. No drawings show how the device would look like before the etching step.
Claim 6 further recites “the first direction”. This feature is also not shown in any drawings.
Claim 7 recites the limitation wherein forming “forming a second film covering at least the region for fabricating the drain; etching the second film to expose a top surface of the substrate”. These steps are not shown in any drawings. No drawings show how the device would look like before the etching step.
Additionally, claim 7 states “a top surface of the substrate” is exposed. However, in Fig. 14, a top surface of the substrate “Si-sub” is never exposed.
Claim 8 recites the limitation wherein forming “forming a second film covering at least the region for fabricating the drain; etching the second film to expose a top surface of the substrate”. These steps are not shown in any drawings. No drawings show how the device would look like before the etching step.
Additionally, claim 8 states “a top surface of the substrate” is exposed. However, in Fig. 16, a top surface of the substrate “Si-sub” is never exposed.
Claim 11 recites “an apparatus for manufacturing a gate-all-around tunneling field-effect transistor (TFET) device”. However, no apparatus is shown in any drawings.
Therefore, the above features must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 8 is objected to because of the following informalities: In line 3, the claim recites, “forming a second film covering at least the region for fabricating the drain”. Examiner believes that the limitation should read, “forming a second film covering at least the region for fabricating the -- source --.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-9 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation wherein forming “a third film of which a thickness is more than or equal to the depth of the recesses; and etching the third film”. Since no drawing is shown, it is unclear, what the device would look like when the thickness of the third film is more than the depth of the recess. Additionally, one of ordinary skill would understand that an etching step is required if the thickness of the third film is greater than the depth of the recess but it is unclear why an etching step is required if the thickness of the third film is equal to the recess. Hence, the claim is indefinite and rejected.
Claim 6 further recites the limitation "the first direction" in line-5. There is insufficient antecedent basis for this limitation in the claim. Hence, the claim is indefinite and rejected. For examination purposes, it will be treated as “a first direction”.
Claim 7 recites the limitation wherein “forming a second film covering at least the region for fabricating the drain” in line 3. Claim 7 depends from claim 1 which recites “a region for fabricating the drain is shielded by another dielectric material” in lines 12-13 of claim 1. It is unclear if the applicant is referring to the “another dielectric material” when reciting “a second film” in claim 7 or does “a second film” in claim 7 refers to a new and different film. Hence, the claim is indefinite and rejected. For examination purposes, “a second film” in claim 7 will be treated as the “another dielectric material” of claim 1. If the applicant believes that the examiner’s treatment of the claim is correct, it is also suggested to re-word the “another dielectric material” to a “-- second -- dielectric material” in claim 1 and correspondingly in claim 7.
Furthermore, regarding claim 7, in line 4, the claim recites that “etching the second film to expose a top surface of the substrate in the region for fabricating the source”. It is unclear if the applicant is suggesting that the substrate comprises both the “BOX” and the “Si-sub” in Fig. 14 or only the “Si-sub”. Examiner notes that the top surface of “Si-sub” is never exposed as shown in Fig. 14. Hence, the claim is indefinite and rejected.
Claim 8 recites the limitation wherein “forming a second film covering at least the region for fabricating the drain” in line 3. Examiner believes that this limitation should be “forming a second film covering at least the region for fabricating the -- source --”, as stated in the claim objection above. Now, Claim 8 depends from claim 1 which recites “wherein a region for fabricating the source is shielded by a dielectric material when fabricating the drain” in lines 11-12 of claim 1. It is unclear if the applicant is referring to the “dielectric material” when reciting “a second film” in claim 8 or does “a second film” in claim 8 refers to a new and different film. Hence, the claim is indefinite and rejected. For examination purposes, “a second film” in claim 8 will be treated as the “dielectric material” of claim 1. If the applicant believes that the examiner’s treatment of the claim is correct, it is also suggested to re-word the “dielectric material” to a “-- first -- dielectric material” in claim 1 and correspondingly in claim 8.
Furthermore, regarding claim 8, in line 4, the claim recites that “etching the second film to expose a top surface of the substrate in the region for fabricating the drain”. It is unclear if the applicant is suggesting that the substrate comprises both the “BOX” and the “Si-sub” in Fig. 16 or only the “Si-sub”. Examiner notes that the top surface of “Si-sub” is never exposed as shown in Fig. 16. Hence, the claim is indefinite and rejected.
Claim 9 recites the limitation "the second film" in line-4. There is insufficient antecedent basis for this limitation in the claim, as “a second film” is not defined in the independent claim 1 or dependent claim 3, from which claim 9 depends on. Hence, the claim is indefinite and rejected. For examination purposes, claim 9 will depend from claim 4 instead of claim 3.
Furthermore, regarding claim 9, in lines 6-7, the claim recites, “removing the dummy gate through wet-etching to expose the at least one sacrificial layer”. Removing the dummy gate (element “Poly” in Fig. 17) does not expose the sacrificial SiGe layer as shown in Fig. 18. Hence, it is unclear what the applicant means by the above limitation and hence rejected. For examination purposes, the limitation will be treated as “removing the dummy gate through wet-etching to expose the -- channel stack --”, as seen in Fig. 18.
Claim 11 recites an apparatus for manufacturing a TFET device which is configured to perform a series of steps comprising “forming”, “etching” and “fabricating” steps. The limitation “configure the apparatus to” implies a deliberate structural design to perform the recited steps. Without knowing the exact configuration of the apparatus, it is unclear how the apparatus is configured to perform the recited steps. Hence, the claim is indefinite and therefore, rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (US 2023/0155009 A1) and further in view of Ok et al. (US 2016/0163809 A1).
Re Claim 1, Reznicek teaches a method for manufacturing a gate-all-around tunneling field- effect transistor (TFET) device (Fig. 15, para [0035]), comprising:
forming, on a substrate (110, Fig. 1, para [0037]), a channel stack (120+130, Fig. 1, paras [0037] – [0040] ) comprising at least one channel layer (120) and at least one sacrificial layer (130) that alternate with each other (see Fig. 1);
forming, on the substrate (110), a dummy gate (210, Fig. 3, paras [0041] – [0042]) astride the channel stack (120+130, Examiner notes that the term “astride” is being treated as the dummy gate being formed near both sides of the channel stack);
forming a first spacer (220, Fig. 3, paras [0041] – [0042]) at a surface of the dummy gate (210);
etching the at least one sacrificial layer to form recesses on side surfaces of the channel stack (etching of layer 130, to form recess where spacers 410 will be formed, Fig 4, para [0046]);
forming second spacers (410, Fig 4, para [0046]) in the recesses, respectively;
fabricating, on the substrate (110) after forming the second spacers (410), a source (610, Fig. 6, paras [0048] – [0049]) and a drain (1110, Fig. 11, para [0054]) separately, wherein a region for fabricating the source (610) is shielded by a dielectric material (1010, Fig. 11, para [0053]) when fabricating the drain (1110, Fig. 11), and a region for fabricating the drain (1110) is shielded by another material (510, Fig. 6) when fabricating the source (610, Fig. 6); and
etching the dummy gate and the at least one sacrificial layer to form a space for a surrounding gate (removal of dummy gate and sacrificial layer 130, para [0057]); and
fabricating a surrounding dielectric-metal gate (1410, Fig. 14, para [0057]) in the space to form the gate-all-around TFET device (see Fig. 14).
Reznicek does not explicitly state the masking layer 510 in Fig. 6 is made of a dielectric material. Reznicek discloses that the masking layer can be an organic planarization layer.
Related art Ok discloses that the organic planarization layer can include a dielectric material (para [0081]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the masking layer of Reznicek can be made of an organic planarization dielectric material as disclosed by Ok. The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 3, Reznicek modified by Ok teaches the method according to claim 1, wherein forming, on the substrate (110, Fig. 3), the dummy gate (210, Fig. 3) astride the channel stack (120+130, Fig. 3) comprises:
forming a first film (depositing the dummy gate, 210, Figs. 2 and 3, para [0041]) covering a surface of the substrate (110) and the channel stack (120+130); and
etching the first film (patterning the dummy stack, para [0041]) according to a pattern of the channel stack to form the dummy gate (dummy gate 210 is etched such that it matches the future patterning step of the channel stack, Figs. 2-3), wherein the dummy gate (210) and the channel stack (120+130) form a stepped structure along a first direction (vertical direction, Fig. 3), and the dummy gate extends across the channel stack along a second direction (horizontal direction, Fig. 3).
Re Claim 4, Reznicek modified by Ok teaches the method according to claim 3, wherein forming the first spacer (220, Fig. 3) at the surface of the dummy gate (210, Fig. 3) comprises:
forming a second film (deposition of spacer 220, para [0041]) which covers the dummy gate (210), the channel stack (120+130), and the substrate (110), wherein etching selectivity between the second film (220) and the first film (210) is not equal to 1 (spacer 220 can be made of silicon oxide while dummy gate 210 can be polycrystalline silicon, and since they are made of different materials, they will have an etching selectivity not equal to 1);
etching the second film (etching of 220 using reactive-ion etching, RIE, para [0041]) to form the first spacer (220) covering side surfaces and a top surface of the dummy gate (210, see Fig. 3), wherein along the first direction (vertical direction, Fig. 3), two ends of the first spacer (220) are aligned with same positions as the side surfaces (see Fig. 3), respectively, of the channel stack (120+130).
Re Claim 5, Reznicek modified by Ok teaches the method according to claim 1, wherein etching the at least one sacrificial layer (130, Fig. 4) to form the recesses on the side surfaces of the channel stack (120+130, Fig. 4) comprises:
etching, from the side surfaces of the channel stack, the at least one sacrificial layer to form the recesses (etching of layer 130, to form recess where spacers 410 will be formed, Fig 4, para [0046]), wherein a depth of each of the recesses is equal to a thickness of the first spacer at a side surface of the dummy gate (the depth of the recess is equal to the thickness of the spacer 410, which is also equal to the thickness of the spacer 220 on the side surface of dummy gate 210, see Fig. 4, para [0046]).
Re Claim 6, Reznicek modified by Ok teaches the method according to claim 1, wherein forming the second spacers (410, Fig 4, para [0046]) within the recesses comprises:
forming, on the side surface of the channel stack (side of 130, Fig. 4), a third film of which a thickness is more than or equal to the depth of the recesses (conformal deposition of dielectric liner, para [0046]); and
etching the third film (isotropic etching of the dielectric liner, para [0046]) to form the second spacers (410, Fig. 4, para [0046]), wherein along the first direction (vertical direction, Fig. 4), an outer surface of each of the second spacers (outer side surface of spacers 410, Fig. 4) is aligned with a same position as a respective sidewall of the at least one channel layer (sidewall of layer 120, Fig. 4).
Re Claim 10, Reznicek modified by Ok teaches the method according to claim 1, wherein fabricating the surrounding dielectric-metal gate (1410, Fig. 14) in the space to form the gate-all-around TFET device comprises:
forming the surrounding dielectric-metal gate (1410, Fig. 14) in the space through atomic layer deposition or vapor deposition (can be formed via atomic layer deposition, para [0057]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (US 2023/0155009 A1) and Ok et al. (US 2016/0163809 A1), and further in view of Mehandru et al. (US 2020/0006559 A1).
Re Claim 2, Reznicek modified by Ok teaches the method according to claim 1, wherein forming, on the substrate (110, Fig. 1), the channel stack (120+130, Fig. 1) comprising the at least one channel layer (120) and the at least one sacrificial layer (130) that alternate with each other comprises:
growing, on a substrate through epitaxy (nanosheet stack is grown epitaxially, para [0040]), at least one layer of silicon germanium (130 can be SiGe, para [0040]) and at least one layer of boron-doped silicon (120 can be boron-doped silicon, para [0040]) that alternate with each other (see Fig. 1), wherein the at least one layer of silicon germanium serves as the at least one sacrificial layer (130 is sacrificial layer, para [0043]), and the at least one layer of boron-doped silicon serves as the at least one channel layer (120 will become the channel layer, para [0043]); and
dry-etching the at least one layer of silicon germanium and the at least one layer of boron-doped silicon to form the channel stack which is a fin extending along a first direction (etching of layers 120 and 130 using reactive-ion etching which is a dry-etch, paras [0042] and [0045], Fig. 3).
Reznicek does not explicitly state that the substrate can be a silicon-on-insulator substrate.
However, related art Mehandru teaches that the substrate can be formed of bulk semiconductor material or silicon-on-insulator structure (para [0048]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to substitute the bulk substrate of Reznicek with a silicon-on-insulator substrate as disclosed by Mehandru, as they are art-recognized alternative materials. The substitution of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (US 2023/0155009 A1) and Ok et al. (US 2016/0163809 A1), and further in view of Krishnan et al. (US 2017/0110539 A1).
Re Claim 7, Reznicek modified by Ok teaches the method according to claim 1, wherein fabricating the source (610, Fig. 6, paras [0048] – [0049]) and the drain (1110, Figs. 11-12, para [0054]) separately comprises:
forming a second film (510, Fig. 6) covering at least the region for fabricating the drain (covering the drain region, compare Figs. 6 and 12);
expose a top surface of the substrate (110) in the region for fabricating the source (see Fig. 5);
growing the source (610, Fig. 6), which is in-situ doped, through epitaxy (epitaxially grown, para [0048]) on the top surface of the substrate (110); and
removing the second film in the region for fabricating the drain (510 is removed, see Fig. 9).
Reznicek does not explicitly state that the second film (510, Fig. 5) was etched to expose a top surface of the substrate in the region for fabricating the source.
Related art, Krishnan discloses a similar process to form the source/drain (Fig. 6), where a mask layer is deposited (para [0035]) over the substrate (10+20, Fig. 6), the nanowire segments (30S, Fig. 6) and gate structure (42+44+50, Fig. 6), followed by patterning the mask layer (patterned mask layer 60, Fig. 6, para [0035]) to expose the region of the substrate where the source (62, Fig. 6) will be formed.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to deposit the mask film conformally and then pattern the mask layer to expose the region of the substrate where the source will be formed, as disclosed by Krishnan. The selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 8, Reznicek modified by Ok teaches the method according to claim 1, wherein fabricating the (610, Fig. 6, paras [0048] – [0049]) and the drain (1110, Figs. 11-12, para [0054]) separately comprises:
forming a second film (1010, Figs. 10-11, para [0053]) covering at least the region for fabricating the source (610);
expose a top surface of the substrate (110) in the region for fabricating the drain (Fig. 10);
growing the drain (1110, Fig. 11), which is in-situ doped, through epitaxy (epitaxially grown, para [0048]) on the top surface of the substrate (110); and
removing the second film in the region for fabricating the source (1010 is removed, see Fig. 12).
Reznicek does not explicitly state that the second film (1010, Fig. 5) was etched to expose a top surface of the substrate in the region for fabricating the drain.
Related art, Krishnan discloses a similar process to form the source/drain (Fig. 6), where a mask layer is deposited (para [0035]) over the substrate (10+20, Fig. 6), the nanowire segments (30S, Fig. 6) and gate structure (42+44+50, Fig. 6), followed by patterning the mask layer (patterned mask layer 60, Fig. 6, para [0035]) to expose the region of the substrate where the source/drain (62, Fig. 6) will be formed.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to deposit the mask film conformally and then pattern the mask layer to expose the region of the substrate where the source/drain will be formed, as disclosed by Krishnan. The selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (US 2023/0155009 A1) and Ok et al. (US 2016/0163809 A1), and further in view of Mehandru et al. (US 2020/0006559 A1) and Le et al. (US 2018/0226490 A1).
Re Claim 9, Reznicek modified by Ok teaches the method according to claim 4, wherein etching the dummy gate (210, Fig. 4) and the at least one sacrificial layer (130, Fig. 4) to form the space for the surrounding gate comprises:
removing the second film over the dummy gate to expose a top surface of the dummy gate (220 over the dummy gate 210 is removed and the top surface of dummy gate 210 is exposed, see Fig. 13);
removing the dummy gate to expose the channel stack (removal of dummy gate 210 and exposing the channel stack, para [0057]); and
removing the at least one sacrificial layer to form the space (removal of sacrificial layers 130, para [0057]).
Reznicek does not explicitly disclose that a planarization step was performed while removing the second film over the dummy gate. However, Reznicek does show that the side surfaces of the second film (220, Fig. 13) is coplanar with the top surface of the dummy gate (top surface of 210, Fig. 13).
Related art, Mehandru discloses that any type of removal of materials during the formation of integrated circuit structures can be done by wet and/or dry etching followed by other processing steps like a planarization or polishing step (para [0043]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the coplanarity of the side surfaces of the second film and the top surface of the dummy gate of the device of Reznicek can be performed by a planarization or polishing step as disclosed by Mehandru. The selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Reznicek also does not explicitly disclose that the dummy gate was removed via wet-etching and that the sacrificial layers were removed via chemical etching or atomic-layer etching.
Related art, Le teaches that the dummy gate can be removed by dry-etch or wet-etch (para [0039]) and the sacrificial layers can be removed via wet chemical etching (para [0042]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to remove the dummy gate and the sacrificial layers of the device of Reznicek via wet-etching and chemical etching respectively, as disclosed by Le. The selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (US 2023/0155009 A1), and further in view of Ok et al. (US 2016/0163809 A1) and Avci et al. (US 2017/0271501 A1).
Re Claim 11, Reznicek teaches manufacturing a gate-all-around tunneling field-effect transistor (TFET) device, comprising:
forming, on a substrate (110, Fig. 1, para [0037]), a channel stack (120+130, Fig. 1, paras [0037] – [0040] ) comprising at least one channel layer (120) and at least one sacrificial layer (130) that alternate with each other (see Fig. 1);
forming, on the substrate (110), a dummy gate (210, Fig. 3, paras [0041] – [0042]) astride the channel stack (120+130, Examiner notes that the term “astride” is being treated as the dummy gate being formed near both sides of the channel stack);
forming a first spacer (220, Fig. 3, paras [0041] – [0042]) at a surface of the dummy gate (210);
etching the at least one sacrificial layer to form recesses on side surfaces of the channel stack (etching of layer 130, to form recess where spacers 410 will be formed, Fig 4, para [0046]);
forming second spacers (410, Fig 4, para [0046]) in the recesses, respectively;
fabricating, on the substrate (110) after forming the second spacers (410), a source (610, Fig. 6, paras [0048] – [0049]) and a drain (1110, Fig. 11, para [0054]) separately, wherein a region for fabricating the source (610) is shielded by a dielectric material (1010, Fig. 11, para [0053]) when fabricating the drain (1110, Fig. 11), and a region for fabricating the drain (1110) is shielded by another material (510, Fig. 6) when fabricating the source (610, Fig. 6); and
etching the dummy gate and the at least one sacrificial layer to form a space for a surrounding gate (removal of dummy gate and sacrificial layer 130, para [0057]); and
fabricating a surrounding dielectric-metal gate (1410, Fig. 14, para [0057]) in the space to form the gate-all-around TFET device (see Fig. 14).
Reznicek does not explicitly state the masking layer 510 in Fig. 6 is made of a dielectric material. Reznicek discloses that the masking layer can be an organic planarization layer.
Related art Ok discloses that the organic planarization layer can include a dielectric material (para [0081]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the masking layer of Reznicek can be made of an organic planarization dielectric material as disclosed by Ok. The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Reznicek also does not disclose an apparatus for manufacturing a gate-all-around tunneling field-effect transistor (TFET) device, comprising:
a memory storing computer-readable instructions, and
a processor, wherein the computer-readable instructions when executed by the processor configure the apparatus.
However, related art, Avci discloses an apparatus for forming a TFET device (para [0078]) that can perform the above functions disclosed by Reznicek. Additionally, the apparatus of Avci can also comprise a memory storing computer-readable instructions (para [0063]) and a processor coupled to the memory that can execute the instructions from the memory to make the TFET device (para [0074]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to configure an apparatus with a memory device and a processor that can execute the instructions from the memory to make the TFET device, as disclosed by Avci, as that would automate the process of manufacturing, thus increasing efficiency and reducing costs, as is the standard practice in the semiconductor manufacturing industry.
Re Claim 12, Reznicek teaches manufacturing a gate-all-around tunneling field-effect transistor (TFET) device:
forming, on a substrate (110, Fig. 1, para [0037]), a channel stack (120+130, Fig. 1, paras [0037] – [0040] ) comprising at least one channel layer (120) and at least one sacrificial layer (130) that alternate with each other (see Fig. 1);
forming, on the substrate (110), a dummy gate (210, Fig. 3, paras [0041] – [0042]) astride the channel stack (120+130), Examiner notes that the term “astride” is being treated as the dummy gate being formed near both sides of the channel stack;
forming a first spacer (220, Fig. 3, paras [0041] – [0042]) at a surface of the dummy gate (210);
etching the at least one sacrificial layer to form recesses on side surfaces of the channel stack (etching of layer 130, to form recess where spacers 410 will be formed, Fig 4, para [0046]);
forming second spacers (410, Fig 4, para [0046]) in the recesses, respectively;
fabricating, on the substrate (110) after forming the second spacers (410), a source (610, Fig. 6, paras [0048] – [0049]) and a drain (1110, Fig. 11, para [0054]) separately, wherein a region for fabricating the source (610) is shielded by a dielectric material (1010, Fig. 11, para [0053]) when fabricating the drain (1110, Fig. 11), and a region for fabricating the drain (1110) is shielded by another material (510, Fig. 6) when fabricating the source (610, Fig. 6); and
etching the dummy gate and the at least one sacrificial layer to form a space for a surrounding gate (removal of dummy gate and sacrificial layer 130, para [0057]); and
fabricating a surrounding dielectric-metal gate (1410, Fig. 14, para [0057]) in the space to form the gate-all-around TFET device (see Fig. 14).
Reznicek does not explicitly state the masking layer 510 in Fig. 6 is made of a dielectric material. Reznicek discloses that the masking layer can be an organic planarization layer.
Related art Ok discloses that the organic planarization layer can include a dielectric material (para [0081]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the masking layer of Reznicek can be made of an organic planarization dielectric material as disclosed by Ok. The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Reznicek also does not disclose a non-transitory computer-readable storage medium, storing computer-readable instructions, wherein the computer-readable instructions when executed by a processor configure an apparatus for manufacturing a gate-all-around tunneling field-effect transistor (TFET) device.
However, related art, Avci discloses a memory which can store computer-readable instructions (para [0063]) and a processor coupled to the memory that can execute the instructions from the memory to make the TFET device (para [0074]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to configure a memory device coupled to a processor that can execute the instructions from the memory to make the TFET device, as disclosed by Avci, as that would automate the process of manufacturing, thus increasing efficiency and reducing costs, as is the standard practice in the semiconductor manufacturing industry.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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