DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Specification 3
III. Claim Rejections - 35 USC § 112 3
A. Claim 7 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 3
IV. Claim Rejections - 35 USC § 103 4
A. Claims 1-3, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2021/198836 as evidenced by US 2023/0113593 (collectively “Yamazaki-836”) in view of WO 2021/0302312 as evidenced by US 2022/0302312 (collectively “Kunitake”). 5
B. Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki-836 in view of Kunitake, as applied to claims 1 and 3 above, and further in view of US 2015/0076491 (“Yamazaki-491”). 15
Conclusion 18
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
III. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
A. Claim 7 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 7 recites the limitation “a first conductor to a third conductor” in line 2. It is unclear what is meant by this limitation.
Claim 7 recites the limitation “a first insulator to a fourth insulator” in lines 2-3. It is unclear what is meant by this limitation.
The lack of clarity is further exacerbated because there is a lack of correspondence between the enumerated insulator layers in claims 1 and 7. In this regard, the first, second, and third insulators in claim 1 appear to correspond to the second, third, and fourth insulator layers, respectively, in claim 7, i.e. the three layers of the gate dielectric. In addition, the fourth and fifth insulators in claim 1 appear to correspond to the fifth and sixth insulators, respectively, in claim 7. Claim 7 includes an extra insulator. Finally, the sixth insulator in claim 1 appears to correspond to the first insulator in claim 7.
Claim 7 recites the limitation, “the second insulator” in each of lines 3, 4, and 19. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation, “the second conductor” in line 11. There is insufficient antecedent basis for this limitation in the claim.
IV. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-3, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2021/198836 as evidenced by US 2023/0113593 (collectively “Yamazaki-836”) in view of WO 2021/0302312 as evidenced by US 2022/0302312 (collectively “Kunitake”).
Each of the US publications are in the respective patent family of the WO publication and are used for translations. As such, all citations will be to the US publications.
Each of the applied prior art references, Yamazaki-836 and Kunitake, has at least one common inventor and a common Assignee with the Instant Application. Based upon the earlier effectively filed date of the reference, each constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In addition to including any one of the statements pursuant to 35 U.S.C. 102(b)(2)(A) through (C), (supra), to overcome each of Yamazaki-836 and Kunitake as prior art available under 35 USC 102(a)(2), each is still applicable as prior art under 35 U.S.C. 102(a)(1) that cannot be excepted under 35 U.S.C. 102(b)(2)(C). In this instance, Applicant may rely on the exception under 35 U.S.C. 102(b)(1)(A) to overcome this rejection under 35 U.S.C. 102(a)(1) by a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application, and is therefore not prior art under 35 U.S.C. 102(a)(1). Alternatively, applicant may rely on the exception under 35 U.S.C. 102(b)(1)(B) by providing evidence of a prior public disclosure via an affidavit or declaration under 37 CFR 1.130(b).
Turning now to the rejection …
Claim 1 reads,
1. (Currently Amended) A semiconductor device comprising:
[1] a metal oxide comprising a channel formation region of a transistor;
[2] a first conductor and a second conductor over the metal oxide;
[3] a first insulator positioned over the metal oxide and between the first conductor and the second conductor;
[4] a second insulator over the first insulator;
[5] a third insulator over the second insulator;
[6] a third conductor over the third insulator;
[7] a fourth insulator positioned between the first conductor and the first insulator;
[8] a fifth insulator positioned between the second conductor and the first insulator; and
[9] a sixth insulator positioned above the first conductor and the second conductor,
[10] wherein the sixth insulator comprises an opening,
[11] wherein the opening comprises a region that is between the first conductor and the second conductor and that overlaps with the metal oxide,
[12] wherein the first insulator, the second insulator, the third insulator, and the third conductor are placed in the opening,
[13a] wherein the first insulator comprises
[13b] a region in contact with a top surface of the metal oxide,
[13c] a region in contact with a side surface of the metal oxide, and
[13d] a region in contact with a sidewall of the opening,
[14] wherein the first insulator is a material through which oxygen is less likely to pass than the second insulator,
[15] wherein the first insulator comprises a region having a thickness of greater than or equal to 1.0 nm and less than 3.0 nm,
[16] wherein the first conductor and the second conductor each comprise a metal element,
[17] wherein the fourth insulator and the fifth insulator comprise the metal element, and
[18] wherein a distance from the first conductor to the first insulator is greater than or equal to a thickness of the first insulator and is less than or equal to a distance from the third conductor to the metal oxide in a cross-sectional view of the transistor in a channel length direction.
With regard to claim 1, Yamazaki-836 discloses, generally in Figs. 1A-1D and 2A-2B,
1. (Currently Amended) A semiconductor device comprising:
[1] a metal oxide 230 comprising a channel formation region of a transistor 200 [¶ 104, 117, 119];
[2] a first conductor 242a and a second conductor 242b [¶¶ 174-178] over the metal oxide 230;
[3] a first insulator 252 [¶¶ 181-188] positioned over the metal oxide 230 and between the first conductor 242a and the second conductor 242b;
[4] a second insulator 250 [¶¶ 189-193] over the first insulator 252;
[5] a third insulator 254 [¶¶ 194-196] over the second insulator 250;
[6] a third conductor 260 [¶¶ 197-201] over the third insulator 254;
[7] – [8] … [not taught] …
[9] a sixth insulator [any one or more of 271, 275, 280 (¶¶ 316, 325, 327)] positioned above the first conductor 242a and the second conductor 242b,
[10] wherein the sixth insulator [any one or more of 271, 275, 280] comprises an opening [opening not labeled],
[11] wherein the opening comprises a region that is between the first conductor 242a and the second conductor 242b and that overlaps with the metal oxide 230,
[12] wherein the first insulator 252, the second insulator 250, the third insulator 254, and the third conductor 260 are placed in the opening,
[13a] wherein the first insulator 252 comprises
[13b] a region in contact with a top surface of the metal oxide 230,
[13c] a region in contact with a side surface of the metal oxide 230, and
[13d] a region in contact with a sidewall of the opening [in each of insulator layers 271, 275, and 280],
[14] wherein the first insulator 252 is a material [e.g. aluminum oxide (¶ 181: “As the insulator 252, a barrier insulating film against oxygen is preferably used.”)] through which oxygen is less likely to pass than the second insulator 250 [e.g. silicon oxide or silicon oxynitride (¶ 189)],
[15] wherein the first insulator 252 comprises a region having a thickness of greater than or equal to 1.0 nm and less than 3.0 nm [¶ 185],
[16] wherein the first conductor 242a and the second conductor 242b each comprise a metal element [e.g. titanium of TiN or tantalum of TaN (¶ 175)],
[17] –[18] … [not taught] …
With regard to features [7], [8], [17], and [18] of claim 1,
[7] a fourth insulator positioned between the first conductor and the first insulator ;
[8] a fifth insulator positioned between the second conductor and the first insulator; and
[17] wherein the fourth insulator and the fifth insulator comprise the metal element, and
[18] wherein a distance from the first conductor to the first insulator is greater than or equal to a thickness of the first insulator and is less than or equal to a distance from the third conductor to the metal oxide in a cross-sectional view of the transistor in a channel length direction.
Yamazaki-836 does not disclose the fourth and fifth insulator and does not consequently teach the limitations of features [7], [8], [17], and [18].
Kunitake, like Yamazaki-836, teaches a thin film transistor (TFT) configured essentially the same and including essentially the same materials (Kunitake: Figs. 1A-1D). Kunitake further teaches a process by which there is an oxygen microwave plasma treatment of an opening formed in the dielectric layer 280 to expose the metal oxide channel 230, which oxidizes in the sidewalls of each of the first 242a and second 242b conductors (made of the same materials at those in Yamazaki-836, e.g. TiN or TaN) exposed in the opening to form insulator regions, 272a and 272b, respectively (Kunitake: ¶¶ 104-110; Figs. 8C, 9B). The thickness of each of the insulator regions, 272a and 272b, in the direction parallel to the plane of the substrate is preferably form 3 to 8 nm (Kunitake: ¶ 101).
The benefit of the insulator regions 272a, 272b is a reduction of oxygen vacancies and, consequently, unwanted carriers in the regions 237a and 237b adjacent to the channel region 236 directly below the gate electrode (Kunitake: Fig. 3; ¶ 101).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform the oxygen microwave plasma treatment in the opening in which the gate electrode is to be formed before the gate dielectric layers 252/250/254 of Yamazaki-836 are formed (i.e. as shown in Yamazaki-836 Fig. 11B), in order to oxidize the sidewalls of each of the first 242a and second 242b conductors exposed in the opening to form insulator regions, 272a and 272b, respectively, in order to remove oxygen vacancies and reduce unwanted carriers in the regions adjacent to the channel portion of the metal oxide layer 230, as taught by Kunitake (Kunitake: ¶ 101). As such, Kunitake may be seen as an improvement to Yamazaki-836 in this aspect. (See MPEP 2143.)
So modified, the limitations of features [7], [8], [17], and [18] are taught, as follows:
[7] a fourth insulator [272a of Kunitake] positioned between the first conductor [242a of Yamazaki-836] and the first insulator [252 of Yamazaki-836];
[8] a fifth insulator [272b of Kunitake] positioned between the second conductor [242b of Yamazaki-836] and the first insulator [252 of Yamazaki-836]; and
[17] wherein the fourth insulator 272a and the fifth insulator 272b comprise the metal element [i.e. the Ti or Ta of the TiN or TaN that is oxidized by the oxygen microwave plasma (Kunitake: ¶¶ 104-110)], and
[18] wherein a distance from the first conductor 242a to the first insulator 252 is greater than or equal to a thickness of the first insulator 252 [1.0 to 3.0 nm (¶ 185)] and is less than or equal to a distance from the third conductor 260 to the metal oxide 230 in a cross-sectional view of the transistor 200 in a channel length direction.
As required by feature [18] of claim 1, the “distance from the first conductor 242a to the first insulator 252 is greater than or equal to a thickness of the first insulator 252” by the thickness of the additional insulator 272a taught by Kunitake, i.e. preferably 3 nm to 8 nm, that is included in Yamazaki-836. As to the distance between the conductor 260 and the metal oxide channel 230, Yamazaki-836 teaches that the thickness of each of the gate dielectric layers 252 and 254 is “further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm” (Yamazaki-836: ¶¶ 185, 196). Yamazaki-836 further teaches that the gate dielectric layer 250 is “further preferably greater than or equal to 0.5 nm and less than or equal to 15.0 nm” (Yamazaki-836: ¶ 190). Thus, the total thickness of the first through third insulators, i.e. 252/250/254, i.e. the distance between the conductor 260 and the metal oxide channel 230, is preferably from 2.5 nm to 21.0 nm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the total thickness of the gate dielectric layers 252/250/254 to be, e.g., 10 nm or 12 nm or 15 nm or 20 nm, because these thicknesses fall within the range suggested in Yamazaki-836. As such, all of the limitations of feature [18] are taught.
This is all of the limitations of claim 1.
With regard to claim 2, Yamazaki-836 further discloses,
2. (Currently Amended) The semiconductor device according to claim 1,
[1] wherein the first insulator 252 [e.g. aluminum oxide (Yamazaki-836, ¶ 181: “As the insulator 252, a barrier insulating film against oxygen is preferably used.”)] is a material through which oxygen and hydrogen are less likely to pass than the second insulator 250 [e.g. silicon oxide or silicon oxynitride (Yamazaki-836: ¶ 189)],
[2] wherein the third insulator 254 is a material through which hydrogen is less likely to pass than the second insulator 250 [e.g. silicon- and nitrogen-containing insulator; Yamazaki-836: ¶ 194: “As the insulator 254, a barrier insulating film against hydrogen is preferably used.” Also ¶ 195],
[3] wherein the first insulator 252 and the second insulator 250 each comprise oxygen [supra],
[4] wherein the second insulator 250 and the third insulator 254 each comprise silicon [supra], and
[5] wherein the third insulator 254 [supra] and the third conductor 260 each comprise nitrogen [layer 260a of 260 may be TiN or TaN (Yamazaki-836: ¶ 199)].
Further with regard to feature [1] of claim 2, the Instant Application uses at least aluminum oxide for the first insulator 252 of the gate dielectric and silicon oxide or silicon oxynitride for the second insulator 250 (¶¶ 133-134, 144, 156 of US 2025/0048676, which is the pre-grant publication of the Instant Application); therefore, the Instant Application admits that aluminum oxide is a barrier for each of oxygen and hydrogen and that silicon oxide and silicon oxynitride allow diffusion of oxygen and nitrogen. As such, the burden of proof is shifted to Applicant to prove the contrary in the insulators 252 and 250 of Yamazaki-836. (See MPEP 2112(I)-(V).)
With regard to claim 3, Yamazaki-836 further discloses,
3. (Currently Amended) The semiconductor device according to claim 1 wherein the first insulator 252 comprises aluminum [i.e. as aluminum oxide (¶ 181, supra)].
With regard to claim 6, Yamazaki-836 modified according to Kunitake, as explained above, further teaches,
6. (Currently Amended) The semiconductor device according to claim 1, wherein the metal element [of the first 242a and second 242b conductors] is tantalum or titanium [as tantalum nitride or titanium nitride (Yamazaki-836: ¶ 175 and Kunitake: ¶¶ 104, 160) that is oxidized to have a TaOx or TiOx region 272a, 272b by the oxygen microwave plasma treatment as taught in Kunitake (¶ 104)].
Claim 7 reads,
7. (Currently Amended) A method for manufacturing a semiconductor device comprising
[1] a metal oxide,
[2] a first conductor to a third conductor,
[3] a first insulator to a fourth insulator,
[4] a fifth insulator positioned between the first conductor and the second insulator, and
[5] a sixth insulator positioned between the second conductor and the second insulator,
the method comprising:
[6] a first step of sequentially forming a metal oxide film and a conductive film;
[7] a second step of processing the metal oxide film and the conductive film into an island shape to form the metal oxide and a conductive layer;
[8] a third step of forming the first insulator;
[9] a fourth step of processing part of the first insulator and part of the conductive layer to form the first conductor, the second conductor, and an opening reaching the metal oxide;
[10] a fifth step of forming a first insulating film in the opening;
[11] a sixth step of forming a second insulating film over the first insulating film;
[12] a seventh step of performing microwave treatment in an atmosphere comprising oxygen;
[13] an eighth step of sequentially forming a third insulating film and a second conductive film; and
[14] a ninth step of forming the second insulator, the third insulator, the fourth insulator, and the third conductor by CMP treatment,
[15] wherein the fifth insulator and the sixth insulator are formed when any one of the fourth step, the fifth step, the sixth step, and the seventh step is performed.
With regard to claim 7, Yamazaki-836 discloses,
7. (Currently Amended) A method for manufacturing a semiconductor device comprising
[1] a metal oxide 230,
[2] a first conductor 242a [, a second conductor 242b, and] to a third conductor 260,
[3] a first insulator [any one or more of 271, 275, 280], a second insulator 252, a third insulator 250, and] to a fourth insulator 254,
[4]-[5] … [not taught] …
the method comprising:
[6] a first step of sequentially forming a metal oxide film 230 and a conductive film 242A [¶¶ 305-315; Figs. 8A-8D];
[7] a second step of processing the metal oxide film 230 and the conductive film 242A into an island shape to form the metal oxide and a conductive layer [¶ 318; Figs. 9A-9D];
[8] a third step of forming the first insulator [any one or more of 271, 275, 280 (¶¶ 316, 325, 327); Figs. 8A-8C and 10A-10D];
[9] a fourth step of processing part of the first insulator 271, 275, 280 and part of the conductive layer 242A to form the first conductor 242a, the second conductor 242b, and an opening reaching the metal oxide 230 [¶ 329; Figs. 11A-11D];
[10] a fifth step of forming a first insulating film 252A in the opening [¶¶ 343-345; Figs. 12A-12D];
[11] a sixth step of forming a second insulating film 250A over the first insulating film 252A [¶¶ 356-359; Figs. 13A-3D];
[12] a seventh step of performing microwave treatment in an atmosphere comprising oxygen [¶¶ 360, 129-132; Figs. 13A-3D];
[13] an eighth step of sequentially forming a third insulating film 254A [¶ 363; Figs. 14A-14D] and a second conductive film 260 [¶ 364; Figs. 15A-15D]; and
[14] a ninth step of forming the second insulator 252, the third insulator 250, the fourth insulator 254, and the third conductor 260 by CMP treatment [¶ 365; Figs. 15A-15D],
[15] … [not taught] …
With regard to features [4], [5], [12], and [15] of claim 7,
[4] a fifth insulator positioned between the first conductor and the second insulator, and
[5] a sixth insulator positioned between the second conductor and the second insulator,
[12] a seventh step of performing microwave treatment in an atmosphere comprising oxygen
[15] wherein the fifth insulator and the sixth insulator are formed when any one of the fourth step, the fifth step, the sixth step, and the seventh step is performed.
As explained under claim 1, above, Yamazaki-836 does not disclose the fifth and sixth insulators, as required by features [4] and [5]. And while Yamazaki-836 discloses a microwave treatment in an atmosphere comprising oxygen, as required by feature [12], Yamazaki-836 does not discuss whether or not said microwave treatment results in the claimed fifth and sixth insulators, as required by feature [15].
As explained above Kunitake teaches forming the fifth 272a and sixth 272b insulators by performing the seventh step of microwave treatment in an atmosphere comprising oxygen that oxidizes the sidewalls of the first 242a and second 242b conductors exposed in the opening in which the gate electrode will subsequently be deposited (supra).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform the oxygen microwave plasma treatment in the opening in which the gate electrode is to be formed before the gate dielectric layers 252/250/254 of Yamazaki-836 are formed (i.e. as shown in Yamazaki-836 Fig. 11B), in order to oxidize the sidewalls of each of the first 242a and second 242b conductors exposed in the opening to form insulator regions, 272a and 272b, respectively, in order to remove oxygen vacancies and reduce unwanted carriers in the regions adjacent to the channel portion of the metal oxide layer 230, as taught by Kunitake (Kunitake: ¶ 101). As such, Kunitake may be seen as an improvement to Yamazaki-836 in this aspect. (See MPEP 2143.)
So modified, the limitations of features [4], [5], [12], and [15] are taught, as follows:
[4] a fifth insulator [272a of Kunitake] positioned between the first conductor [242a of Yamazaki-836] and the second insulator [252 of Yamazaki-836], and
[5] a sixth insulator [272b of Kunitake] positioned between the second conductor [242b of Yamazaki-836] and the second insulator [252 of Yamazaki-836],
[12] a seventh step of performing microwave treatment in an atmosphere comprising oxygen [of Kunitake used in Yamazaki-836]
[15] wherein the fifth insulator [272a of Kunitake] and the sixth insulator [272b of Kunitake] are formed when any one of the fourth step, the fifth step, the sixth step, and the seventh step is performed.
This is all of the limitations of claim 7.
B. Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki-836 in view of Kunitake, as applied to claims 1 and 3 above, and further in view of US 2015/0076491 (“Yamazaki-491”).
Claims 4 and 5 read,
4. (Currently Amended) The semiconductor device according to claim 3 wherein the metal oxide has a concentration gradient with an increasing concentration of aluminum from a bottom surface of the metal oxide toward the top surface of the metal oxide.
5. (Currently Amended) The semiconductor device according to claim 4 wherein the metal oxide comprises at least indium, aluminum, and zinc.
The prior art of Yamazaki-836 in view of Kunitake, as explained above, teaches each of the features of claims 1 and 3.
Yamazaki-836 further discloses that the metal oxide semiconductor layer 230 may be made of indium aluminum zinc oxide (hereafter “InAlZnO” not indicative of stoichiometry) (Yamazaki-836: ¶¶ 119, 228, 241, ).
Yamazaki-836 does not disclose that the metal oxide semiconductor layer 230 has an aluminum gradient increasing from its bottom surface toward its upper surface, i.e. toward the interface with the gate dielectric 252/250/254.
Yamazaki-491, like Yamazaki-836, teaches a TFT having a metal oxide semiconductor channel layer 106 that may be InAlZnO (Yamazaki-491: Fig. 1; ¶¶ 14-16, 23-26, 101), wherein the overlying gate dielectric layer 112 may be aluminum oxide (Yamazaki-491: ¶ 116). Yamazaki-491 further teaches that the concentration of aluminum in the InAlZnO semiconductor oxide layer 106 may have a gradient of Al increasing from the first oxide 102 toward the gate dielectric 112, as follows:
[0013] One embodiment of the present invention is (1) a semiconductor device including a first insulating film [102], an oxide semiconductor film [106] over the first insulating film, a second insulating film [112] over the oxide semiconductor film, and a conductive film [104] overlapping with the oxide semiconductor film with one of the first insulating film and the second insulating film provided between the oxide semiconductor film and the conductive film. A composition of the oxide semiconductor film changes continuously between the first insulating film and the second insulating film.
[0015] Another embodiment of the present invention is (3) the semiconductor device described in (1) in which the oxide semiconductor film [106] contains indium, an element M (aluminum, gallium, yttrium, or tin), and zinc; and the oxide semiconductor film has an element M concentration gradient that increases toward the second insulating film [112].
[0065] FIG. 1A is a cross-sectional view illustrating a structure of a transistor. The transistor in FIG. 1A includes an insulating film 102 over a substrate 100, a semiconductor film 106 over the insulating film 102, a conductive film 116a and a conductive film 116b which are in contact with a top surface of the semiconductor film 106, an insulating film 112 over the semiconductor film 106, the conductive film 116a, and the conductive film 116b, and a conductive film 104 overlapping with the semiconductor film 106 with the insulating film 112 provided therebetween. The conductive film 104 serves as a gate electrode of the transistor.
[0125] The insulating film 112 functions as a gate insulating film of a transistor.
(Yamazaki-491: ¶¶ 13, 15, 65, 125; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the InAlZnO semiconductor channel layer 230 of Yamazaki-836 to have an Al concentration gradient increasing from a bottom surface of the metal oxide 230, i.e. near the interface with insulating layer 224, toward the top surface of the metal oxide, i.e. near the interface of the gate dielectric layer 252/250/254, in order to control the electron affinity, i.e. said Al gradient correspondingly producing a decreasing electron affinity gradient toward the gate dielectric 252/250/254, which results in improved electrical characteristics, including higher reliability than without the Al gradient, as explained in Yamazaki-491:
[0135] In FIG. 2B, the electron affinity of the semiconductor film 106 changes continuously between the insulating film 102 and the insulating film 112. Specifically, the electron affinity of the semiconductor film 106 includes a gradient that decreases toward the interface between the semiconductor film 106 and the insulating film 112. The electron affinity has a discontinuous point at the interface between the insulating film 102 and the semiconductor film 106.
[0136] Thus, in the case of employing the band diagram in FIG. 2B, the electrical characteristics of the transistor can be sometimes improved as compared to the case of employing the band diagram in FIG. 1C. For example, interface states due to junction of different kinds of materials, damage in deposition, entry of impurities, or the like are generated in some cases at the interface between the semiconductor film 106 and the insulating film 112.
[0137] With the band diagram in FIG. 2B, a channel region is apart from a region including the interface states. That is, the band diagram is not easily affected by the interface states; thus, in the transistor with the band diagram, a decrease in on-state current due to the interface states is less likely to occur. Thus, a transistor with high on-state current and a low S value is obtained. In addition, when there is an energy difference between the region including the interface states and the channel region, carriers are not easily trapped in the interface states. Thus, variation in the electrical characteristics due to the interface states does not easily occur, so that a transistor with high reliability is obtained.
(Yamazaki-491: ¶¶ 135-137; emphasis added)
Note that the increase in Al corresponds to a decrease in In (with Zn remaining about the same through the thickness) in the InAlZnO semiconductor oxide layer, which results in the decreasing electron affinity with increasing Al concentration and correspondingly decreasing In concentration, as explained in Yamazaki-491 (at ¶¶ 371-375; Fig. 26).
This is all of the limitations of claims 4 and 5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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