DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 13, 14 and 15 are objected to because of the following informalities:
Claim 13 recites the limitation “wherein one side of the device is 100 pm or less by forming the isolation groove in the compound semiconductor functional layer” in lines 2-4.
Claim 14 recites the limitation “wherein one side of the device is 100 pm or less by forming the isolation groove in the compound semiconductor functional layer” in lines 2-4
Claim 15 recites the limitation “wherein one side of the device is 100pmor less by forming the isolation groove in the compound semiconductor functional layer” in lines 2-4.
However, there is lack of clarity in the meaning and the scope for the limitation “wherein one side of the device is 100pmor less by forming the isolation groove in the compound semiconductor functional layer” in claims 13, 14 and 15 for the following reasons:
It is not clear that what “one side of the device is 100 pm or less” entails. Does it mean that the length or width of the device that in one side after the etching performed to form the isolation groove? Does it mean the height of the device that in one side after the etching performed to form the isolation groove? And etc. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 10, 13, 16, 19 and 23-25 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10, 12, 13, 18, 21 and 22 of copending Application No. 18/696,117 in view of Chae et al. (US 2019/0164945).
Although the conflicting claims are not identical, the scope of the claimed limitations of the instant application as claimed in claims 10-25 is similar to that of the claimed limitations of copending Application No. 18/696,117 as claimed in claims 10-25. Therefore, the claims are not patentably distinct from each other.
The instant application:
10. A method for manufacturing a bonded semiconductor wafer, the method comprising the steps of: epitaxially growing an etching stop layer on a starting substrate; producing an epitaxial wafer by epitaxially growing an epitaxial layer having a compound semiconductor functional layer on the etching stop layer; forming an isolation groove to form a device in the compound semiconductor functional layer by a dry etching method; performing roughening etching on a surface of the epitaxial layer, being the opposite side of the starting substrate, thereby making surface roughness thereon to have 0.1 μm or more in an arithmetic average roughness Ra; bonding a visible light-transmissive substrate of a different material from a material of the epitaxial layer to the surface opposite to the starting substrate of the epitaxial layer via a visible light-transmissive thermosetting bonding material; and removing the starting substrate.
13. The method for manufacturing a bonded semiconductor wafer according to claim 10, wherein one side of the device is 100 μm or less by forming the isolation groove in the compound semiconductor functional layer.
16. The method for manufacturing a bonded semiconductor wafer according to claim 10, wherein the device is a micro-LED structure having a light emitting layer and a window layer.
19. The method for manufacturing a bonded semiconductor wafer according to claim 13, wherein the device is a micro-LED structure having a light emitting layer and a window layer.
23. The method for manufacturing a bonded semiconductor wafer according to claim 10, wherein the visible light-transmissive substrate is any one of sapphire, quartz, glass, SiC, LiTaO3, or LiNbO3.
24. The method for manufacturing a bonded semiconductor wafer according to claim 10, wherein the visible light-transmissive thermosetting bonding material is any one or more materials of benzocyclobutene, silicone resin, epoxy resin, spin-on-glass, polyimide, or fluororesin.
25. The method for manufacturing a bonded semiconductor wafer according to claim 10, wherein the visible light-transmissive thermosetting bonding material has a thickness of 0.01 μm or more and 0.6 μm or less.
Co-pending Application No. 18/696,117:
10. A method for manufacturing a bonded semiconductor wafer, the method comprising the steps of: epitaxially growing an etching stop layer on a starting substrate; epitaxially growing a compound semiconductor functional layer on the etching stop layer; forming an isolation groove for forming a device in the compound semiconductor functional layer by a dry etching method; etching on a surface of the isolation groove by a wet etching method; bonding a visible light-transmissive substrate of a different material from a material of the compound semiconductor functional layer to the compound semiconductor functional layer via a visible light-transmissive thermosetting bonding member; and obtaining a bonded semiconductor wafer by removing the starting substrate from the compound semiconductor functional layer bonded to the visible light-transmissive substrate.
12. The method for manufacturing a bonded semiconductor wafer according to claim 10, wherein in the step of forming the isolation groove, the isolation groove is formed in the compound semiconductor functional layer, and thus, one side of the device is 100 μm or less.
13. The method for manufacturing a bonded semiconductor wafer according to claim 10, wherein the device is a micro-LED structure having a light emitting layer and a window layer.
13. The method for manufacturing a bonded semiconductor wafer according to claim 10, wherein the device is a micro-LED structure having a light emitting layer and a window layer.
18. The method for manufacturing a bonded semiconductor wafer according to claim 10, wherein the visible light-transmissive substrate is selected from the group consisting of sapphire, quartz, glass, SiC, LiTaO3, and LiNbO3.
21. The method for manufacturing a bonded semiconductor wafer according to claim 14, wherein the visible light-transmissive thermosetting bonding member is selected from the group consisting of BCB, silicone resin, epoxy resin, SOG, polyimide, and amorphous fluoropolymer.
22. The method for manufacturing a bonded semiconductor wafer according to claim 10, wherein a thickness of the visible light-transmissive thermosetting bonding member is 0.01 μm or more and 0.6 μm or less.
With respect of limitation “performing roughening etching on a surface of the epitaxial layer, being the opposite side of the starting substrate, thereby making surface roughness thereon to have 0.1 μm or more in an arithmetic average roughness Ra,” co-pending application does not claim. However, forming such rough structure on a surface of an epitaxial layer neither novel nor non obvious.
Chae et al. disclose etching of upper surface epitaxial layer (41) to form roughened surface (41a) in order to form convex-concave region on the epitaxial layer in order to scatter light (Chae et al. Fig. 7 and Paragraphs [0341] - [0342]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to provide co-pending application claimed invention with performing roughening etching on a surface of the epitaxial layer, being the opposite side of the starting substrate as taught by Chae et al. in order to scatter light.
This is a provisional nonstatutory double patenting rejection.
Allowable Subject Matter
Claims 11, 12, 14, 15, 17, 18, 20-22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Liao et al. (US 2005/0287687), Seo et al. (US 2014/0339566) and TSUJIMOTO et al. (US 2016/0211425) also disclose similar inventive subject matter.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM.
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/BROOK KEBEDE/
Primary Examiner, Art Unit 2894
/BK/
June 12, 2026
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