DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, and 5 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Yamazaki et al. (US-20200126992-A1; Yamazaki).
Regarding claim 1, Yamazaki discloses a semiconductor device comprising: a first transistor comprising a first oxide (Fig. 2B/6/20, 230_2c of 600; ¶136); a second transistor comprising a second oxide (Fig. 2B/6/20, 230_2b of 601; ¶135); and a third oxide (Fig. 2B/6/20, 276; ¶224), wherein the first oxide comprises a channel formation region (Fig. 6, 234; ¶140) of the first transistor, wherein the second oxide comprises a channel formation region (Fig. 6, 234; ¶140) of the second transistor, wherein the third oxide comprises the same material (aluminum oxide) as the first oxide and the second oxide, wherein the third oxide is separated from the first oxide and the second oxide, wherein in a top view, the third oxide is positioned between the first oxide and the second oxide, wherein the third oxide is positioned in the same layer as the first oxide and the second oxide, and wherein the third oxide is not configured to be a channel formation region of any transistor.
Regarding claim 3, Yamazaki discloses a semiconductor device comprising; a circuit, wherein the circuit comprises a transistor (Fig. 2B/6/20, 200b; ¶136)and a first region (Fig. 2B/6/20, 600; ¶136,353) comprising the transistor, wherein the transistor comprises a first oxide (Fig. 2B/6/20, 230_2c of 600; ¶136) in a channel formation region (Fig. 6, 234; ¶140), wherein a second oxide (Fig. 2B/6/20, 276; ¶224) is provided in the first region, wherein the second oxide comprises the same material (aluminum oxide) as the first oxide, wherein the second oxide is separated from the first oxide, wherein the first region is shaped into a square (Fig. 2A, a square region around 200b) in a top view so as to comprise at least the channel formation region of the transistor, wherein an area of the first region and an area occupied by one transistor converted from a transistor density of the circuit are equal to each other, wherein the first region overlaps with at least part of the first oxide and the second oxide in the top view, and wherein the second oxide (Fig. 2B/6/20, 276; ¶224) is not configured to be a channel formation region of any transistor.
The feature, "wherein the first region is shaped into a square" does not appear to limit the structure. Applicant draws (chooses) a square region (Fig. 2A, 13) around a transistor (Fig. 2A, 200) and oxide (Fig. 2A, 230d) between adjacent transistors/oxides (Fig. 2A, 200/230d) in a top view. However the physical region is not in a square shape. Yamazaki discloses a similar device where one of ordinary skill in the art would be able to draw a square around a transistor/oxide between adjacent transistor/oxides in an array.
Regarding claim 5, Yamazaki discloses a semiconductor device comprising; a circuit, wherein the circuit comprises a transistor (Fig. 2B/6/20, 200b; ¶136) and a first region (Fig. 2B/6/20, 600; ¶136,353) comprising the transistor, wherein the transistor comprises a first conductor (Fig. 2b/6/20, 260_2b of 600; ¶136) configured to be a gate electrode and an oxide (Fig. 2B/6/20, 230_2c of 600; ¶136) comprising a channel formation region, wherein a second conductor (Fig. 2b/6/20, 240; ¶132) not overlapping with the oxide is provided in the first region, wherein the second conductor comprises the same material (¶205 & 226) as the first conductor, wherein the second conductor is separated from the first conductor, wherein the first region is shaped into a square (Fig. 2A, a square region drawn around 200ab) in a top view so as to comprise at least the channel formation region (Fig. 6, 234; ¶191) of the transistor, wherein an area of the first region and an area occupied by one transistor converted from a transistor density of the circuit are equal to each other, wherein the first region overlaps with at least part of the first conductor and the second conductor in the top view, and wherein the second conductor is not configured to be a gate electrode of any transistor.
The feature, "wherein the first region is shaped into a square" does not appear to limit the structure. Applicant draws (chooses) a square region (Fig. 2A, 13) around a transistor (Fig. 2A, 200) and oxide (Fig. 2A, 230d) between adjacent transistors/oxides (Fig. 2A, 200/230d) in a top view. However the physical region is not in a square shape. Yamazaki discloses a similar device where one of ordinary skill in the art would be able to draw a square around a transistor/oxide between adjacent transistor/oxides in an array.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US-20200126992-A1; Yamazaki).
Regarding claim 2, Yamazaki discloses the semiconductor device according to claim 1, wherein a gate electrode (Fig. 2b/6/20, 260 of 600; ¶160) of the first transistor comprises a region with a width (Fig. 6, 234; ¶191 10nm-30nm) greater than or equal to 1 nm and less than or equal to 20 nm in a cross-sectional view of the first transistor in a channel length direction, and wherein a gate electrode (Fig. 2b/6/20, 260 of 601; ¶160) of the second transistor comprises a region with a width (Fig. 6, 234; ¶191 10nm-30nm) greater than or equal to 1 nm and less than or equal to 20 nm in a cross-sectional view of the second transistor in a channel (Fig. 6, 234; ¶191) length direction.
The channel region is discloses to have a width of 10nm-30nm. The Figure 6 discloses the gate length (width) to be approximately the same as the channel width. 30nm is greater than 20 nm . Therefore the gate length (width) is greater than the claimed range.
While, Yamazaki does not expressly teaches the range of greater than or equal to 1 nm and less than or equal to 20 nm some of its value ” 10nm-30nm” fall within the claim range of greater than or equal to 1 nm and less than or equal to 20 nm, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “10nm-30nm”, as disclosed in prior art, to arrive at the recited limitation.
Regarding claim 4, Yamazaki discloses the semiconductor device according to claim 3, wherein a gate electrode (Fig. 2b/6/20, 260 of 600; ¶160) of the transistor comprises a region with a width (Fig. 6, 234; ¶191 10nm-30nm) greater than or equal to 1 nm and less than or equal to 20 nm in a cross-sectional view of the transistor in a channel (Fig. 6, 234; ¶191) length direction.
The channel region is discloses to have a width of 10nm-30nm. The Figure 6 discloses the gate length (width) to be approximately the same as the channel width. 30nm is greater than 20 nm . Therefore the gate length (width) is greater than the claimed range.
While, Yamazaki does not expressly teaches the range of greater than or equal to 1 nm and less than or equal to 20 nm some of its value ” 10nm-30nm” fall within the claim range of greater than or equal to 1 nm and less than or equal to 20 nm, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “10nm-30nm”, as disclosed in prior art, to arrive at the recited limitation.
Regarding claim 6, Yamazaki discloses the semiconductor device according to claim 5, wherein the first conductor (Fig. 2b/6/20, 260 of 600; ¶160) comprises a region with a width (Fig. 6, 234; ¶191 10nm-30nm) greater than or equal to 1 nm and less than or equal to 20 nm in a cross-sectional view of the transistor in a channel (Fig. 6, 234; ¶191) length direction.
The channel region is discloses to have a width of 10nm-30nm. The Figure 6 discloses the gate length (width) to be approximately the same as the channel width. 30nm is greater than 20 nm . Therefore the gate length (width) is greater than the claimed range.
While, Yamazaki does not expressly teaches the range of greater than or equal to 1 nm and less than or equal to 20 nm some of its value ” 10nm-30nm” fall within the claim range of greater than or equal to 1 nm and less than or equal to 20 nm, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “10nm-30nm”, as disclosed in prior art, to arrive at the recited limitation.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US-20200126992-A1; Yamazaki) in view of Endo (US-20180061989-A1; Endo ).
Regarding claim 7, Yamazaki discloses the semiconductor device according to claim 3 but is silent on wherein the transistor density of the circuit is higher than or equal to 1 Tr/um2 and lower than or equal to 1000 Tr/um2.
Modern transistors are nanoscale devices where hundreds are disposed within a square um area. Yamazaki discloses a transistor array but is silent on the transistor density.
Endo discloses forming a transistor array where transistors are formed with a density of higher than or equal to 0.01/μm.sup.2 and lower than or equal to 2500/μm.sup.2, (¶98)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to have a high density of transistors for optimal driving power and integration. While, Endo does not expressly teaches the range of higher than or equal to 1 Tr/um2 and lower than or equal to 1000 Tr/um2 some of its value ” higher than or equal to 0.01/μm.sup.2 and lower than or equal to 2500/μm.sup.2” fall within the claim range of higher than or equal to 1 Tr/um2 and lower than or equal to 1000 Tr/um2 some of its value, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “higher than or equal to 0.01/μm.sup.2 and lower than or equal to 2500/μm.sup.2”, as disclosed in prior art, to arrive at the recited limitation.
Regarding claim 8, Yamazaki discloses the semiconductor device according to claim 6 but is silent on wherein the transistor density of the circuit is higher than or equal to 1 Tr/pm2 and lower than or equal to 1000 Tr/pm2.
Modern transistors are nanoscale devices where hundreds are disposed within a square um area. Yamazaki discloses a transistor array but is silent on the transistor density.
Endo discloses forming a transistor array where transistors are formed with a density of higher than or equal to 0.01/μm.sup.2 and lower than or equal to 2500/μm.sup.2, (¶98)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to have a high density of transistors for optimal driving power and integration. While, Endo does not expressly teaches the range of higher than or equal to 1 Tr/um2 and lower than or equal to 1000 Tr/um2 some of its value ” higher than or equal to 0.01/μm.sup.2 and lower than or equal to 2500/μm.sup.2” fall within the claim range of higher than or equal to 1 Tr/um2 and lower than or equal to 1000 Tr/um2 some of its value, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “higher than or equal to 0.01/μm.sup.2 and lower than or equal to 2500/μm.sup.2”, as disclosed in prior art, to arrive at the recited limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
Prosecution Insights