DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Preliminary Amendment
Claims 1-11 and 13-14 have been amended; and claims 1-14 are currently pending.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statements filed on 04/07/2026 and 06/04/2024 has been acknowledged and signed copies of the PTO-1449 are attached herein.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 13 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 13 recites that “the recrystallisation heat treatment is implemented at a temperature below 700oC., preferentially below 550oC., and advantageously below 500oC.” The disclosure as originally filed describes the recrystallisation heat treatment only at temperature of 600oC and below (see Pars [0040] and [0076]). The recited upper bound of “below 700oC” therefore encompasses a range (greater than 600oC up to 700oC) not described in a manner sufficient to show possession of the claimed invention at the time of filing. Applicant is required to show specific support or amend to a supported range.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Batude et al. (US 2016/0020153 A1, hereinafter “Batude”) in view of Bedell et al. (US 2008/0258220 A1, hereinafter “Bedell”).
In regards to claim 1, Batude discloses (See, for example, Fig. 1B) a method for producing a microelectronic device provided with a plurality of superimposed levels of electronic components, the method comprising, in this order, steps consisting in:
a) producing a structure comprising a support (2) provided with at least one component of a first level of components, said support (2) being surmounted by an insulating layer (4), the insulating layer (4) itself being surmounted by a semiconductor layer (See for example, 6, Par [0041]) of a second level, said semiconductor layer including at least one lower sublayer (6a1, 6a2 of layer 6) in contact with said insulating layer (4) and an upper sublayer (24b, 26b) disposed on the lower sublayer (6a1, 6a2), a first of said lower and upper sublayers (24b, 26b) being made from crystalline semiconductor material (See, Par [0051]) while a second of said lower (6a1, 6a2) and upper sublayers is made from amorphous semiconductor material (See, Par [0049]) then
b) forming at least one transistor (gate pattern 16, and gate dielectric 10) gate block (16) on said semiconductor layer (6), then
c) forming, on either side of the gate block (16), by implantation(s) of dopants (“implantation…”, See Par [0055]-[000056]) in said semiconductor layer (“on each side of the channel zone 18,…”, See Par [0056]) doped regions on either side of a semiconductor region located facing the gate block and provided for accommodating a channel of said transistor (See, Pars [0055]-[0059]), then
d) implementing at least one heat treatment so as to implement a recrystallisation of the second amorphous sublayer while using the first crystalline sublayer as a start region of a crystalline front while implementing an activation (See, for example, Par [0083]) of said dopants (“…recrystallisation front 24c.. and one recrystallisation front 26c… by applying a given temperature ….betweebn 400oC and 600oC…”, See for example, Pars [0061]-[0064]).
However, Batude is silent about the order of step (a) and step (b), completion of step (a) prior to forming the gate block in step (b).
Bedell while disclosing heat treatments to minimize implant induced amorphization teaches (See, for example, Figs. 3C-3E) that an implantation performed on the semiconductor-on-insulator structure at a stage before any gate block is formed, See, for example, Fig. 3C. Ion implant 550 being applied to semiconductor-on-insulator substrate 560 comprising semiconductor-on-insulator layer 570 on box layer 580 on base substrate 590, See Par [0034]. No gate yet present. Bedell further teaches that ion implant 600 being applied to partially completed FET 610 and 700 already provided with gate blocks 630 and 740, respectively, over channel regions 650/760 and strained source/drain regions 660/770. See, for example, Fig. 3D-3E, and Par [0035].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to perform Batude’s amorphous implantation prior to forming the gate block in the order recited in claim 1 by Bedell’s teaching that implantation of the SOI structure is carried out before gate block formation as an art recognized alternative to an after
block formation implant. The result of doing so is entirely predictable: the same amorphous/crystalline sublayer structure taught by Batude is simply present upon completion of step a), before the gate block of step b). The selection of the order in which the recited process steps are performed, where each step and the resulting structure are taught by the prior art, would have been obvious absent a showing of new or unexpected results. MPEP 2144.04(IV)(C ); KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421, 82 USPQ2d 1385, 1397 (2007).
In regards to claim 2, Batude as modified above discloses (See, for example, Fig. 1B) wherein the step a) comprises an amorphisation implantation of a thickness of said semiconductor layer of the second level so as to form said second sublayer made from amorphous semiconductor material (“… in-depth or partially buried amorphisation step to regions 24, 26 so as to form in-depth zones 24a, 26a of amorphous material starting from regions 24 and 26 and regions 6a1, 6a2 of amorphous material in the layer 6…” See, for example, Par [0049]; “it might be possible to complete the amorphisation using at least one implantation step.”, See Par [0055]).
In regards to claim 4, Batude as modified above discloses (See, for example, Figs. 1B-1C, Bedell) wherein, at the step a), the first sublayer, made from amorphous material (100), is the upper sublayer, said second sublayer, made from crystalline material (80’), being the lower sublayer.
In regards to claim 5, Batude as modified above discloses (See, for example, Fig. 1B) that wherein, at the step a), the first sublayer, which is amorphous (6a1, 6a2), is the lower sublayer, said second sublayer, which is crystalline (24b, 26b), being the surface sublayer.
In regards to claims 6-9, Batude as modified above discloses all limitations of claim 5 except that
wherein the formation of the structure at the step a) comprises substeps consisting in: providing a first substrate provided with said first level of components, bonding, on the first substrate, a second substrate provided with said semiconductor layer, removing a portion of the second substrate while preserving the semiconductor layer bonded to the first substrate (claim 6);
the step a) furthermore comprises, prior to said bonding, a step of amorphisation of said semiconductor layer of the second level so as to form the second semiconductor sublayer (claim 7);
wherein, prior to said bonding, an implantation of the first substrate is implemented so as to create a weakening region, the amorphisation of said semiconductor layer being implemented after said creation of said weakening region (claim 8); and
wherein an etching stop layer is arranged on the second substrate and up against said semiconductor layer, the removal of a portion of the second substrate furthermore comprising a selective etching of the etching stop layer with respect to said semiconductor layer (claim 9).
It is well known in the art of manufacturing semiconductor device that semiconductor layer transfer by molecular (direct) bonding followed by removal of a donor-substrate portion, including the Smart Cut type technique of forming a weakening (fractured) region by hydrogen and/or helium implantation, and use of a SiGe etch-stop layer for thickness control of a transferred silicon layer, were each readily well-known and conventional in the SOI fabrication.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to employ such conventional transfer techniques because tt is well known in the art of manufacturing semiconductor device that semiconductor layer transfer by molecular (direct) bonding followed by removal of a donor-substrate portion, including the Smart Cut type technique of forming a weakening (fractured) region by hydrogen and/or helium implantation, and use of a SiGe etch-stop layer for thickness control of a transferred silicon layer, were each readily well-known and conventional in the SOI fabrication.
In regards to claim 10, Batude as modified above discloses (See, for example, Fig. 1B) that wherein the method comprises, after the step b):
the formation of insulating spacers (20a, 20B) on either side of the gate block (16), the step c) of forming the doped regions comprises an implantation of dopants implemented after said formation of the insulating spacers (“a doping step takes place before, during or after the amorphization and before recrystallisation step”, See Par [0022] and claim 4).
In regards to claim 11, Batude as modified above discloses (see, for example, Fig. 1B) a gowth of semiconductor blocks on either side of the gate block on the semiconductor layer is performed before step d).
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have the a growth of semiconductor blocks on either side of the gate block on the semiconductor layer after step d), reversing the order of the processing steps because performing the epitaxial block growth after recrystallization is an obvious rearrangement of processing steps yielding the predictable result of raised source/drain regions. MPEP 2144.04(IV)(C ); KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421, 82 USPQ2d 1385, 1397 (2007).
In regards to claim 13, Batude as modified above discloses (See, for example, Fig. 1B) wherein the recrystallisation heat treatment is implemented at a temperature below 700° C., preferentially below 550° C., and advantageously below 500° C (See, for example, Par [0064]; and Claim 6).
In regards to claim 14, Batude as modified above discloses (See, for example, Fig. 1B) wherein, the component of the first level is produced in a layer of semiconductor material (6 on dielectric layer 4, See Par [0042]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Batude in view of Bedell as applied to claim 11 above, and further in view of Wang et al. (US 2004/0248369 A1, hereinafter “Wang”).
In regards to claim 12, Batude as modified above discloses (See, for example, Fig. 1B) that wherein, at the step a), the first sublayer, which is amorphous (65a1, 6a2), is the lower sublayer, said second sublayer, which is crystalline (24b, 26b), being the surface sublayer.
Batude is silent about the method furthermore comprising, after the step d) and prior to the growth of said semiconductor blocks, the removal of non-doped surface regions.
Wang while disclosing a method of fabricating a MOSFET device teaches prior to the selective epitaxial growth (SEG) of raised, single-crystalline source/drain structure, a top portion of the exposed source/drain surface is removed by etching, the raised single-crystalline source/drain then being selectively grown upon the exposed source/drain region (See, Pars [0010], [0016]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to remove the non-doped crystalline surface region of Batude after step d) and prior to the regrowth of the raised source/drain blocks of Wang because this would help lower the source/drain contact resistance.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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