Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1 it is unclear whether the limitation “support substrate” as recited in line 4 is referring to “a support substrate” as recited in line 2 of claim 1. It is further unclear whether the limitation “an active layer of single-crystal SiC…” as recited in lines 7 and 8 of claim 1 is referring to the limitation “an active layer of single-crystal silicon carbide” as recited in line 3 of claim 1.
With regards to claim 15, it is not clear whether the final structure requires the first layer.
Regarding claim 16, it is not clear whether the limitations “back face of the structure”… “a front face of the structure” as recited in line 2 of claim 16 is referring to “a semiconductor structure” as recited in line 1 of claim 16.
Regarding claim 19 it not clear whether the limitation “a semiconductor structure” as recited in claim 19 is the same as the one in claim 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Maekawa et al., WO 2021020574.
Regarding claim 1, as best the examiner is able to ascertain the claimed invention Maekawa discloses (figs. 2, 3a-3c, 4a-4b and related text) a method of manufacturing a semiconductor structure (10) including a support substrate of polycrystalline silicon carbide (12a/12b) and an active layer of single-crystal silicon carbide (11), the method comprising: forming a support substrate including a stack of a first layer (12b) of polycrystalline SiC and a second layer of polycrystalline SiC (12a), bonding a donor substrate (21) including the active layer of single-crystal SiC (11) of polytype 4H (description of 3b) to face of the support substrate, and transferring the active layer (11) onto the support substrate (12b).
Maekawa does not explicitly disclose the first layer of the polycrystalline SiC is mainly of polytype 3C or the second layer of polycrystalline SiC (12a) is mainly of polytype 4H.
In different embodiments of (figs. 23 and refer to the description of the figs.) Maekawa discloses the use of 3C type polycrystalline to make a substrate without a void and furthermore Maekawa discloses the second layer (513) of polycrystalline SiC) is mainly of polytype 4H (refer to the process of forming 501, where the buffer layer 513 is made of 4H SiC) to achieve desired physical properties and reduce cost.
Maekawa’s different embodiments are analogous art because they both are directed the process of making a substrate and one of ordinary skill in the art would have had a reasonable expectation of success to modify Maekawa’s different embodiments because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Maekawa to include the 3C and 4H as taught by the different embodiment Maekawa to make a substrate without a void and to achieve desired physical properties and reduce cost.
The combined process would have a face of polytype 4H the support substrate as claimed.
Regarding claim 2, Maekawa as modified discloses forming of the support substrate comprises growing the first layer (11) on a seed substrate (21) and growing the second layer (12a) on the first layer (12b).
Regarding claim 3, Maekawa discloses forming of the support substrate successively comprises growing the second layer (12b) on a seed substrate (22/21), growing the first layer (12a) on the second layer (12b) and removing the seed substrate (22/21) in order to expose a face of the second layer (12a) for the bonding of the donor substrate (figs. 3a-3e).
Regarding claim 4, Maekawa discloses the seed substrate (21) is a single-crystal SiC substrate mainly of polytype 4H (fig. 3 description).
Regarding claim 5, Maekawa discloses growing the first layer (12a) to a thickness of between 1 and 20 µm (Maekawa discloses 12a may have a thickness 0.5 µm or more) and growing the second layer (12b) to a thickness of between 80 and 350 µm Maekawa discloses 12b may be formed to a thickness of 350 µm).
Regarding claim 6, Maekawa discloses growing the first layer (11) to a thickness of between 80 and 200 µm (1 µm or more includes 80-200 µm) and growing the second layer (12b) to a thickness of between 150 and 270 µm (to a thickness of 350 µm).
Regarding claim 7, Maekawa discloses growing the first layer (12a) and of the second layer (12b) is carried out by chemical vapor deposition (CVD, abstract and description figs. 3a-3e).
Regarding claim 8, Maekawa discloses growing the first layer (11) is carried out at a temperature of between 1100 and 1500°C, preferably between 1200 and 1400°C (CVD temperature, refer to the growth 3C polycrystalline SiC, 310).
Regarding claim 9, Maekawa does not explicitly disclose the second layer (12a) at a temperature of between 1500 and 2600°C.
Parameters such as growth in the art of semiconductor process are subject to routine experimentation and optimization to achieve the desired device characterization during fabrication.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize appropriate growth temperature to meet the requirements of the particular design, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233
Regarding claim 10, Maekawa discloses introducing dopants during the growth of the first layer and of the second layer (refer to the growth 310 and 313).
Regarding claim 11, Maekawa discloses the bonding of the donor substrate (21/22) to the face of polytype 4H and/or 6H of the support substrate comprises is bonding the donor substrate directly to the face of polytype 4H of the support substrate (12).
Regarding claim 12, Maekawa discloses the bonding of the donor substrate (21) to the face of polytype 4H and/or 6H of the support substrate comprises bonding the donor substrate to the face of polytype 4H the support substrate via a bonding layer (22).
Regarding claim 16, as best the examiner is able to ascertain the claimed invention, Maekawa discloses (figs. 2, 3a-3e and related text) a semiconductor structure successively comprising, from its back face of the structure to it’s a front face of the structure: a first layer (12b) of polycrystalline SiC,; a second layer (12a) of polycrystalline SiC ; and an active layer (11) of single-crystal SiC of polytype 4H or 6H (refer to the description of 11).
Maekawa does not explicitly disclose polytype 3C for the first layer or the second layer mainly of polytype 4H.
In different embodiments of (figs. 23 and refer to the description of the figs.) Maekawa discloses the use of 3C type polycrystalline substrate (310) to make a substrate without a void and furthermore Maekawa discloses the second layer (513) of polycrystalline SiC (that is mainly of polytype 4H (refer to the process of forming 501, where the buffer layer 513 is made of 4H SiC) to achieve desired physical properties and reduce cost.
Maekawa’s different embodiments are analogous art because they both are directed the process of making a substrate and one of ordinary skill in the art would have had a reasonable expectation of success to modify Maekawa’s different embodiments because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Maekawa to include the 3C and 4H as taught by the different embodiments Maekawa to make a substrate without a void and to achieve desired physical properties and reduce costs.
Regarding claim 17, Maekawa as modified disclose the first layer (12b) has a thickness of between 80 and 350 µm (to a thickness of 350 µm); and the second layer (12a) has a thickness of between 1 and 20 µm (Maekawa discloses 12a may have a thickness 0.5 µm or more).
Regarding claim 18, Maekawa discloses the first layer (11) has a thickness of between 80 and 200 µm (1 µm or more includes 80-200 µm); and the second layer (12b) has a thickness of between 150 and 270 µm (to a thickness of 350 µm).
Regarding claim 19, as best the examiner is able to ascertain the claimed invention Maekawa discloses an electronic device (MOSFET device fig. 7), the semiconductor structure according to one of claims 16 in or on the active layer (refer to fig. 26).
Regarding claim 20, Maekawa discloses the at least one electronic component comprises a diode (Schottky diode or MOSFET).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM.
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/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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