DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 103 3
A. Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0254324 (“Kaji”) in view of either of JP 2010-64918 (“JP ‘918”). 3
B. Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0254324 (“Kaji”) in view of JP 2010-64919 (“JP ‘919”). 9
Conclusion 14
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0254324 (“Kaji”) in view of either of JP 2010-64918 (“JP ‘918”).
Note that the text citations to JP ‘918 are from the machine translation provided by Applicant in the IDS filed 06/13/2024.
Claim 9 reads,
9. (Original) A method of manufacturing a silicon carbide substrate, the method comprising:
[1] growing a silicon carbide crystal on a seed crystal by sublimating source material powder in which carbon powder is added to silicon carbide powder; and
[2a] performing heat treatment on the grown silicon carbide crystal, wherein in the performing heat treatment,
[2b] a heat treatment temperature is 1900° C to 2100° C, and
[2c] a heat treatment time is 20 hours or more.
With regard to claim 9, Kaji discloses, generally in Figs. 3-5,
9. (Original) A method of manufacturing a silicon carbide substrate [Fig. 3], the method comprising:
[1] growing a silicon carbide crystal 53 on a seed crystal 51 by sublimating source material powder 52 in which carbon powder is added to silicon carbide powder [¶¶ 37-42; step S30 in Fig. 3]; and
[2a]-[2c] … [not taught] …
With regard to features [2a]-[2c] of claim 9, Kaji does not perform a heat treatment on the grown SiC crystal 53.
With regard to claim 9, JP ‘918 teaches, generally in Figs. 1, 2(a)-2(b),
[1] growing a silicon carbide crystal 40 on a seed crystal 13 by sublimating source material powder 5 …[comprising]… silicon carbide powder 5 [¶¶ 35-41]; and
[2a] performing heat treatment [i.e. annealing] on the grown silicon carbide crystal 41(=13/40), wherein in the performing heat treatment,
[2b] a heat treatment temperature is 1900° C to 2100° C [¶ 54: i.e. 2000° C], and
[2c] a heat treatment time is 20 hours or more [¶ 54, i.e. 30 hr].
With regard to features [2a]-[2c] of claim 9, JP ‘918 states,
[0054] <Silicon Carbide Single Crystal Ingot Annealing Step>
After the seed crystal holding member (lid portion) 22 is removed, the silicon carbide single crystal ingot 41[=13/40] is preferably annealed before the silicon carbide single crystal wafer production step. For example, the annealing temperature is set to 2000° C., and this state is maintained for 30 hours. Accordingly, the residual stress of silicon carbide single crystal ingot 41[=13/40] can be further reduced. When the residual stress of silicon carbide single crystal ingot 41 is sufficiently reduced, this step may not be performed.
(JP ‘918: ¶ 54; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to anneal the SiC ingot 53 of Kaji for 30 hours at 2000° C in order to reduce residual stress in the SiC ingot 53 caused by sublimation growth, as taught by JP ‘918. As such, JP ‘918 may be seen as an improvement to Kaji in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 9.
In the alternative, JP ‘918 may be seen as the primary reference. JP ‘918 lacks only including carbon powder along with the SiC powder for the raw material powder that is sublimated to grow the SiC ingot 40.
Kaji teaches that the raw material includes carbon powder added to SiC powder (Kaji: ¶¶ 37, 46-50) in the raw material powder. Kaji explains that the benefit is to reduce carbon vacancies, which improves majority carrier lifetimes:
[0047] In the case in which a silicon carbide substrate has a short carrier lifetime, sufficient conductivity modulation does not occur, resulting in the failure to provide a bipolar semiconductor device having a low on-resistance. One way to prolong the carrier lifetime is to reduce carbon vacancies, which cause crystal defects serving as a lifetime killer. An effective way to reduce carbon vacancies in the single crystal 53 of silicon carbide is to increase the ratio of carbon to silicon. Accordingly, adding carbon powder to silicon carbide powder to make the raw material powder 52 is a preferable measure for reducing carbon vacancies.
(Kaji: ¶ 47; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include carbon powder along with the SiC powder in the raw material of JP ‘918, in order to reduce carbon vacancies in the grown SiC ingot 40, as taught by Kaji. As such, Kaji may be seen as an improvement to JP ‘918 in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 9.
Claims 1 and 4 read,
1. (Original) A silicon carbide substrate comprising
[1] a main surface, wherein the main surface is constituted of an outer peripheral region that is a region within 5 mm from an outer edge of the main surface and a central region surrounded by the outer peripheral region,
[2] a standard deviation of lifetimes of minority carriers in the central region is 0.7 ns or less, and
[3] when a standard deviation of lifetimes of the minority carriers in the central region before a process of heating to a temperature of 1600° C to 1900° C is performed is defined as a first standard deviation and a standard deviation of lifetimes of the minority carriers in the central region after the process is performed is defined as a second standard deviation, a value obtained by subtracting the first standard deviation from the second standard deviation is 10% or less of the first standard deviation.
4. (Currently Amended) The silicon carbide substrate according to claim 1, wherein the value obtained by subtracting the first standard deviation from the second standard deviation is 5% or less of the first standard deviation.
With regard to claims 1 and 4, Kaji discloses, generally in Figs. 1 and 2
1. (Original) A silicon carbide substrate 9 comprising
[1] a main surface 91, wherein the main surface 91 is constituted of an outer peripheral region 92 that is a region within 5 mm from an outer edge of the main surface and a central region 93 surrounded by the outer peripheral region 92 [¶¶ 23, 26],
[2] a standard deviation of lifetimes of minority carriers in the central region is 0.7 ns or less [¶¶ 26-30], and
[3] … [not taught] …
4. … [not taught] …
With regard to feature [3] of claim 1 and claim 4, Kaji does not discuss making the measurement of the standard deviation of minority carrier lifetimes before and after a process of heating the SiC substrate to a temperature of 1600° C to 1900° C. However, this limitation is merely a statement of intended use, i.e. the intended testing of a SiC substrate to determine the claimed property of the relative standard deviations in the minority carrier lifetimes before and after the heating process. The substrate cannot simultaneously have said property both before and after the claimed heating process. In other words, the SiC substrate before the claimed heating process is a different SiC substrate after the claimed heating process because the claimed heating process changes at least the minority carrier lifetime. As such, all that is required is that a prior art SiC substrate be capable of showing the claimed property recited in feature [3] of claim 1 and claim 4.
With this in mind, it is held, absent evidence to the contrary, that the SiC substrate of Kaji/JP ‘918 formed by cutting the SiC ingot into wafers (Kaji: ¶¶ 44-46 and JP ‘918: ¶ 55), inherently meets the property of the first and second standard deviations because the Instant Application admits that it is (1) the incorporation of extra carbon from the added carbon power during the sublimation growth of the SiC ingot ( Instant Specification: ¶ 56)—as also taught in Kaji (Kaji: ¶ 47, supra)—and (2) the annealing at a temperature in a range of 1900 ℃ to 2100 ℃ for 20 hours or longer (Instant Specification: ¶¶ 64-68)—as also taught in JP ‘918 (supra)—that results in the property recited in feature [3] of claim 1. As such, the burden of proof is shifted to Applicant to prove the contrary, i.e. that the SiC wafer of Kaji/JP ‘918 does not have the property claimed in feature [3] of claim 1 and claim 4. (See MPEP 2112(I)-(V).)
This is all of the limitations of claims 1 and 4.
With regard to claims 2, 3, and 5-7, Kaji further discloses,
2. (Original) The silicon carbide substrate according to claim 1, wherein a concentration of majority carriers in the central region is 1×1017 cm-3 or more [Kaji: abstract; ¶¶ 5, 12, 13, 25, claim 1].
3. (Original) The silicon carbide substrate according to claim 2, wherein the majority carriers are n-type carriers [Kaji: ¶ 25].
5. (Currently Amended) The silicon carbide substrate according to claim 1, wherein an average value of the lifetimes of the minority carriers in the central region is 200 ns or less [¶ 28, i.e. less than 100 ns and preferably less than 50 ns].
6. (Currently Amended) The silicon carbide substrate according to claim 1, wherein the main surface has a diameter of 100 mm or more [¶¶ 16, 17, 24].
7. The silicon carbide substrate according to claim 1, wherein the main surface is inclined at an off-angle in an off-direction relative to a {0001} plane, and the off-angle is more than 0° and 8° or less [¶¶ 23, 44].
With regard to claim 8, Kaji modified according to JP ‘918, as explained under claim 1, above, further teaches,
8. (Currently Amended) A method of manufacturing a silicon carbide semiconductor device, the method comprising:
[1] preparing the silicon carbide substrate according to claim 1 [supra]; and
[2] processing the silicon carbide substrate [¶¶ 13, 24, 25].
While Kaji does not discuss any specific processing, Kaji states that the substrate is for the formation of semiconductor devices such as MOSFET and SBD (Kaji: ¶¶ 13, 24, 25). As such, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to process the substrate in order to make a semiconductor device such as a MOSFET or SBD, as suggested in Kaji.
This is all of the limitations of claim 8.
B. Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0254324 (“Kaji”) in view of JP 2010-64919 (“JP ‘919”).
Note that the text citations to JP ‘919 are from the machine translation attached to this Office action and all citations to the drawings are from the original Japanese publication, also attached to this Office action.
Claim 9 reads,
9. (Original) A method of manufacturing a silicon carbide substrate, the method comprising:
[1] growing a silicon carbide crystal on a seed crystal by sublimating source material powder in which carbon powder is added to silicon carbide powder; and
[2a] performing heat treatment on the grown silicon carbide crystal, wherein in the performing heat treatment,
[2b] a heat treatment temperature is 1900° C to 2100° C, and
[2c] a heat treatment time is 20 hours or more.
With regard to claim 9, Kaji discloses, generally in Figs. 3-5,
9. (Original) A method of manufacturing a silicon carbide substrate [Fig. 3], the method comprising:
[1] growing a silicon carbide crystal 53 on a seed crystal 51 by sublimating source material powder 52 in which carbon powder is added to silicon carbide powder [¶¶ 37-42; step S30 in Fig. 3]; and
[2a]-[2c] … [not taught] …
With regard to features [2a]-[2c] of claim 9, Kaji does not perform a heat treatment on the grown SiC crystal 53.
JP ‘919 teaches a process of annealing a SiC ingot to remove stresses cause by the sublimation growth process from a SiC powder on a seed crystal powder, which prevents cracking when cutting the ingot into wafers (abstract; p. 2, line 33-p. 3, line 12; section entitled “Annealing process” on pp. 12-19). With regard to features [2a]-[2c], JP ‘919 states,
(Example 5)
Using a mixture of silicon carbide powder and graphite (graphite) powder as filler powder, increasing the mass ratio of graphite (graphite) in the vicinity of the silicon carbide single crystal ingot and increasing the mass ratio of silicon carbide in the surrounding area in the same manner as in Example 1, except that the annealing temperature was 2000 ° C. and the annealing treatment time was 20 hours.
(JP ‘919 translation: p. 24, lines 3-8,; emphasis added)
Table 1 on page 20 of the Japanese publication shows that the above anneal reduced the cracks to 3%.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to anneal the SiC ingot 53 of Kaji for 20 hours at 2000° C in order to reduce residual stress in the SiC ingot 53 caused by sublimation growth, as taught by JP ‘919 (abstract; p. 2, line 33-p. 3, line 12; section entitled “Annealing process” on pp. 12-19). As such, JP ‘919 may be seen as an improvement to Kaji in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 9.
Claims 1 and 4 read,
1. (Original) A silicon carbide substrate comprising
[1] a main surface, wherein the main surface is constituted of an outer peripheral region that is a region within 5 mm from an outer edge of the main surface and a central region surrounded by the outer peripheral region,
[2] a standard deviation of lifetimes of minority carriers in the central region is 0.7 ns or less, and
[3] when a standard deviation of lifetimes of the minority carriers in the central region before a process of heating to a temperature of 1600° C to 1900° C is performed is defined as a first standard deviation and a standard deviation of lifetimes of the minority carriers in the central region after the process is performed is defined as a second standard deviation, a value obtained by subtracting the first standard deviation from the second standard deviation is 10% or less of the first standard deviation.
4. (Currently Amended) The silicon carbide substrate according to claim 1, wherein the value obtained by subtracting the first standard deviation from the second standard deviation is 5% or less of the first standard deviation.
With regard to claims 1 and 4, Kaji discloses, generally in Figs. 1 and 2
1. (Original) A silicon carbide substrate 9 comprising
[1] a main surface 91, wherein the main surface 91 is constituted of an outer peripheral region 92 that is a region within 5 mm from an outer edge of the main surface and a central region 93 surrounded by the outer peripheral region 92 [¶¶ 23, 26],
[2] a standard deviation of lifetimes of minority carriers in the central region is 0.7 ns or less [¶¶ 26-30], and
[3] … [not taught] …
4. … [not taught] …
With regard to feature [3] of claim 1 and claim 4, Kaji does not discuss making the measurement of the standard deviation of minority carrier lifetimes before and after a process of heating the SiC substrate to a temperature of 1600° C to 1900° C. However, this limitation is merely a statement of intended use, i.e. the intended testing of a SiC substrate to determine the claimed property of the relative standard deviations in the minority carrier lifetimes before and after the heating process. The substrate cannot simultaneously have said property both before and after the claimed heating process. In other words, the SiC substrate before the claimed heating process is a different SiC substrate after the claimed heating process because the claimed heating process changes at least the minority carrier lifetime. As such, all that is required is that a prior art SiC substrate be capable of showing the claimed property recited in feature [3] of claim 1 and claim 4.
With this in mind, it is held, absent evidence to the contrary, that the SiC substrate of Kaji/JP ‘918 formed by cutting the SiC ingot into wafers (Kaji: ¶¶ 44-46 and JP ‘918: ¶ 55), inherently meets the property of the first and second standard deviations because the Instant Application admits that it is (1) the incorporation of extra carbon from the added carbon power during the sublimation growth of the SiC ingot ( Instant Specification: ¶ 56)—as also taught in Kaji (Kaji: ¶ 47, supra)—and (2) the annealing at a temperature in a range of 1900 ℃ to 2100 ℃ for 20 hours or longer (Instant Specification: ¶¶ 64-68)—as also taught in JP ‘919 (supra)—that results in the property recited in feature [3] of claim 1. As such, the burden of proof is shifted to Applicant to prove the contrary, i.e. that the SiC wafer of Kaji/JP ‘919 does not have the property claimed in feature [3] of claim 1 and claim 4. (See MPEP 2112(I)-(V).)
This is all of the limitations of claims 1 and 4.
With regard to claims 2, 3, and 5-7, Kaji further discloses,
2. (Original) The silicon carbide substrate according to claim 1, wherein a concentration of majority carriers in the central region is 1×1017 cm-3 or more [Kaji: abstract; ¶¶ 5, 12, 13, 25, claim 1].
3. (Original) The silicon carbide substrate according to claim 2, wherein the majority carriers are n-type carriers [Kaji: ¶ 25].
5. (Currently Amended) The silicon carbide substrate according to claim 1, wherein an average value of the lifetimes of the minority carriers in the central region is 200 ns or less [¶ 28, i.e. less than 100 ns and preferably less than 50 ns].
6. (Currently Amended) The silicon carbide substrate according to claim 1, wherein the main surface has a diameter of 100 mm or more [¶¶ 16, 17, 24].
7. The silicon carbide substrate according to claim 1, wherein the main surface is inclined at an off-angle in an off-direction relative to a {0001} plane, and the off-angle is more than 0° and 8° or less [¶¶ 23, 44].
With regard to claim 8, Kaji modified according to JP ‘919, as explained under claim 1, above, further teaches,
8. (Currently Amended) A method of manufacturing a silicon carbide semiconductor device, the method comprising:
[1] preparing the silicon carbide substrate according to claim 1 [supra]; and
[2] processing the silicon carbide substrate [¶¶ 13, 24, 25].
While Kaji does not discuss any specific processing, Kaji states that the substrate is for the formation of semiconductor devices such as MOSFET and SBD (Kaji: ¶¶ 13, 24, 25). As such, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to process the substrate in order to make a semiconductor device such as a MOSFET or SBD, as suggested in Kaji.
This is all of the limitations of claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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