Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“A memory device including a pillar transistor having alternating aluminum-content semiconductor layers”
Because the new title more accurately identifies the key features recited in the independent claims, namely a memory device including a pillar transistor and semiconductor layers having an alternating aluminum-content arrangement. This title is therefore more descriptive of the claimed invention.
Abstract
The abstract is objected to because of the following informalities:
Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. In particular, there is no place in a single paragraph abstract for paragraph numbers. Therefore, the paragraph number (e.g., "(90)", "(S103)", "(S110)") in the present Abstract should be deleted.
Furthermore, the abstract of the disclosure is objected to because it is written in legal terminology which is too similar to claim language. In particular, legal phraseology such as the term “comprising”, “said” and “wherein” which are commonly used to define the limitations and scope pf patent claims, should generally be avoided in U.S. patent abstracts because the purpose of the abstract is not to define the patent claims, but to provide the reader with a clear and concise summary. The abstract should use plain language to describe the invention's technical problem, solution, and principal use. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” etc. Correction is required. See MPEP § 608.01(b).
Appropriate correction is required.
Claim Objections
Claims 9, 10 and 12 are objected to as containing informalities.
Specifically, claim 9 recites "(90)," claim 10 recites "(S103)," and claim 12 recites "(S110)." Reference characters are not necessary in the claims and should be removed.
Claim 16 is objected to as containing informalities.
the chemical formulas "Y2O3, TiO2, HfO2, ZrO2, and La2O3." Applicant is required to properly format the chemical formulas, e.g., Y₂O₃, TiO₂, HfO₂, ZrO₂, and La₂O₃, throughout the application.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 1, the claim recites:
"...the plurality of semiconductor layers is configured such that an aluminum content changes between each consecutive layer such that every second layer has a lower aluminum content than the neighboring mutually opposite layers thereof."
The phrase "the neighboring mutually opposite layers thereof" renders the claim indefinite because it is unclear which layers are being referenced by this limitation.
Specifically, the term "the neighboring" does not provide an objective boundary for determining which layers are encompassed by the limitation. It is unclear whether "the neighboring" refers only to layers immediately adjacent to a given layer or whether it also includes layers separated by one or more intervening layers.
Further, the phrase "mutually opposite layers" lacks a reasonably certain meaning in the context of a plurality of semiconductor layers stacked in an axial direction. The claim does not explain what relationship makes layers "mutually opposite," nor does it identify which layers are considered opposite to one another. As a result, one of ordinary skill in the art would not be able to determine with reasonable certainty which layers must possess a higher aluminum content than the recited "every second layer."
Accordingly, the metes and bounds of the claimed aluminum-content relationship among the semiconductor layers are not reasonably certain, and the scope of the claim cannot be determined with reasonable certainty.
Applicant may amend the claim to positively recite the intended layer relationship, for example:
"...wherein every second layer has a lower aluminum content than the immediately adjacent layers on opposite sides thereof,".
Regarding claims 2-8 and 15-16, because of their dependency on claim 1, these claims are also objected for the reasons set forth above with respect to claim 1.
Regarding claim 9, the claim recites:
"...wherein the plurality of semiconductor layers of the p-doped pillar segment is configured such that an aluminum content changes between each consecutive layer such that every second layer has a lower aluminum content than the neighboring mutually opposite layers thereof."
The phrase "the neighboring mutually opposite layers thereof" renders the claim indefinite because it is unclear which layers are being referenced by this limitation.
Specifically, the term "the neighboring" does not provide an objective boundary for determining which layers are encompassed by the limitation. It is unclear whether "the neighboring" refers only to layers immediately adjacent to a given layer or whether it also includes layers separated by one or more intervening layers.
Further, the phrase "mutually opposite layers" lacks a reasonably certain meaning in the context of a plurality of semiconductor layers stacked in the axial direction of the pillar. The claim does not explain what relationship makes layers "mutually opposite," nor does it identify which layers are considered opposite to one another. As a result, one of ordinary skill in the art would not be able to determine with reasonable certainty which layers must possess a higher aluminum content than the recited "every second layer."
Accordingly, the metes and bounds of the claimed aluminum-content relationship among the semiconductor layers are not reasonably certain, and the scope of the claim cannot be determined with reasonable certainty.
Applicant may amend the claim to positively recite the intended relationship between the layers, for example:
"...wherein every second layer has a lower aluminum content than the immediately adjacent layers on opposite sides thereof,".
Regarding claims 10-14 and 17-18, because of their dependency on claim 9, these claims are also objected for the reasons set forth above with respect to claim 9.
Allowable Subject Matter
Claims 1-18 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1. The closest prior art of record includes Harada et al. (US 20220367468) and Carlson et al. (US 20190013404) teach some of claimed features as follows:
Harada discloses a memory device including a substantially vertical semiconductor pillar extending between source and bit lines. The semiconductor pillar includes source, body, and drain regions arranged along the axial direction of the pillar to form a vertical pillar transistor. Harada further teaches surrounding gate structures configured to control current through the pillar transistor during memory operations, as well as methods for fabricating such vertical pillar memory devices. See, e.g., the Abstract, [0085]-[0086], and Figs. 1 and 5A-5H.
Further, Carlson discloses a vertical charge-storage memory architecture including a vertically extending semiconductor channel, a charge-storage layer, and dielectric layers separating the semiconductor channel from the charge-storage layer. Carlson further discloses a memory transistor including a control gate, charge-storage layer, charge-blocking layer, tunnel dielectric, semiconductor channel, and source/drain regions. See, e.g., [0019]-[0023] and Figs. 1 and 1A, and [0046]-[0049] and Fig. 12.
Accordingly, the prior art teaches numerous aspects of the presently claimed memory device, including a vertical pillar transistor, source/body/drain regions arranged along a semiconductor pillar, surrounding gate structures, and charge-storage memory structures.
However, neither Harada nor Carlson, alone or in combination, teaches or suggests a memory device in which at least one p-doped pillar segment of the pillar transistor comprises a plurality of stacked AlGaN or GaN semiconductor layers having a varying aluminum-content arrangement along the axial direction of the pillar. The prior art further fails to teach or suggest incorporating such a III-nitride multilayer pillar segment into a vertical charge-storage memory device.
Accordingly, the prior art of record fails to teach or suggest the claimed combination. Therefore, independent claim 1, together with claims depending therefrom, would be allowable over the prior art of record upon resolution of the outstanding rejection under 35 U.S.C. § 112(b) and correction of the noted informalities.
Regarding claim 9. The closest prior art of record includes Harada et al. (US 20220367468) and Carlson et al. (US 20190013404) teach some of claimed features as follows:
Harada discloses methods of fabricating vertical semiconductor pillar memory devices including forming semiconductor pillars, forming source, body, and drain regions along the semiconductor pillars, and forming surrounding gate structures associated with the pillar transistors. See, e.g., [0085]-[0086] and Figs. 5A-5H.
Carlson discloses methods of fabricating vertical charge-storage memory devices including forming a vertically extending semiconductor channel, depositing dielectric layers and charge-storage material adjacent the semiconductor channel, and forming control gates to produce charge-storage memory cells. See, e.g., [0019]-[0023], [0046]-[0049], and Figs. 1, 1A, and 12.
Accordingly, the prior art teaches numerous aspects of the claimed manufacturing method, including forming vertical semiconductor pillars, pillar transistors, surrounding gate structures, and charge-storage memory cells.
However, neither Harada nor Carlson, alone or in combination, teaches or suggests forming a p-doped pillar segment from a plurality of stacked AlGaN or GaN semiconductor layers having a varying aluminum-content arrangement along the axial direction of the pillar, followed by forming a charge-storage memory cell utilizing the pillar transistor.
Accordingly, the prior art of record fails to teach or suggest the claimed manufacturing method. Therefore, independent claim 9, together with claims depending therefrom, would be allowable over the prior art of record upon resolution of the outstanding rejection under 35 U.S.C. § 112(b) and correction of the noted informalities.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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