DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 04/02/2026.
Applicant's election with traverse of Group II, claims 23-30 in the reply filed on 04/02/2026 is acknowledged. The traversal is on the ground(s) that the subject matter of all claims is sufficiently related that a thorough search for the subject matter of any one Group of claims would encompass a search of all of the remaining claims. This is not found persuasive because the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 23 recites, “an RTA method” in step (2). The claim is indefinite because the meets and bounds of an RTA treatment are unclear. An RTA, rapid thermal annealing, process must have same range of temperatures, process gases, ramping rates, processing times etc. Furthermore, “rapid” is a relative term, and is indefinite because it is unclear what distinguishes an RTA treatment from a conventional annealing process. For the purposes of expediating examination, any thermal annealing which forms a carbon diffusion layer is interpreted as being “rapid.” The same argument applies to dependant claims 24-30 which incorporates the same indefinite claim language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 23, 25, 27, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qu et al (US 2023/0212782) in view of Murphy et al (US 2006/0267024) and Li et al (CN 108538972A), an English computer translation is provided.
Qu et al teaches a method for producing a semiconductor substrate including a silicon single crystal substrate 1 having a front surface and a back surface; and a semiconductor thin film formed on the front surface, the method comprising the steps of: (1) providing a silicon single crystal substrate 1 having a front surface and a back surface (Fig 1; [0011]-[0027]; (2) implanting carbon into at least the front surface and the back surface of the silicon single crystal substrate by an RTA method to form a carbon diffusion layer 5 with a carbon concentration of 5E+16 atoms/cm3 or more (Fig 1; [0027]-[0107] teaches a carbon diffusion layer has a concentration of 1x1017 atom/cm3 with a thickness of 2 mm or more using RTA at 1150-1400°C for 1 to 60 seconds and CH4/Ar gases); and (3) growing a semiconductor thin film (epitaxial layer 6) containing by vapor deposition on the front surface of the silicon single crystal substrate into which the carbon diffusion layer is formed (Fig 1; [0052]-[0081], [0106]).
Qu et al teaches forming a Si epitaxial film on the Si substrate after forming the carbon diffusion layer which form a SiC layer (Abstract; [0011]-[0027]).
In a method of forming a semiconductor structure, Murphy et al teaches a silicon wafer 1 (Fig 1a), implanting carbon ion and performing a heat treatment to form a SiC layer 4 (Fig 1b-1e), and depositing an epitaxial layer 5 (Fig 1f) of GaN, AlGaN, or InAlGaN layer on the SiC layer 4b. (See Abstract; [0023]-[0046]; Fig 1).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Qu by depositing a gallium nitride layer, as taught by Murphy et al, to form a useful semiconductor device structure.
The combination of Qu et al and Murphy et al teaches deposition of GaN on a substrate, however does not explicitly teach vapor deposition.
In a method forming GaN films, Li et al teaches a Si substrate and preparing GaN by MOCVD on the Si substrate; depositing a pre-laid Al layer with a thickness of 1-1.5 nm at 800-980°C using trimethylaluminum (TMAl), a AlN thin film with a thickness of 100-300 nm at 900-1000°C using TMAl and ammonia; and depositing a GaN layer using trimethylgallium and ammonia at 900-1200°C (CT [0007], [0019]-[0030]). Li et al teaches growing high quality low defect density GaN which can be used for LED and other fields.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Qu et al and Murphy et al by using the method of vapor deposition of GaN on a Si substrate, as taught by Li et al, to produce a high quality low defect density GaN.
Referring to claim 25, the combination of Qu et al, Murphy et al and Li et al teaches the carbon diffusion layer has a thickness of 2 mm (Qu [0107]).
Referring to claim 27 and 29, the combination of Qu et al, Murphy et al and Li et al teaches depositing a pre-laid Al layer with a thickness of 1-1.5 nm at 800-980°C using trimethylaluminum (TMAl) (Li CT [0026]). Overlapping ranges are prima facie obvious (MPEP 2144.05)
Claim(s) 24, 26, 28 and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qu et al (US 2023/0212782) in view of Murphy et al (US 2006/0267024) and Li et al (CN 108538972A), an English computer translation is provided, as applied to claim 23 above, and further in view of Kononchuk et al (US 2003/0106482).
The combination of Qu et al, Murphy et al and Li et al teaches all of the limitations of claim 24, as discussed above, except the silicon substrate has a resistivity of 100 ohm-cm or more, and oxygen concentration of 7E+17 atom/cm3 or less. Qu et al broadly teaches any silicon single-crystal substrate can be used regardless of a defective region of crystals, a diameter, conductivity (type and resistivity), etc ([0051]).
In a method of making a high resistivity silicon wafer, Kononchuk et al teaches A high-resistivity silicon wafer comprising: a wafer substrate having a resistivity of 100 ohm-cm or greater, and an interstitial oxygen content of 8 ppma or less (abstract; [0012],Claim 23). Overlapping ranges are prima facie obvious (MPEP 2144.05). Kononchuk et al teaches the wafer has high resistivity, increased gettering ability, and is resistant to slip dislocations ([0013]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Qu et al, Murphy et al and Li et al by using a silicon substrate having a resistivity of 100 ohm-cm or more, and oxygen concentration of 7E+17 atom/cm3 or less, as taught by Kononchuk et al, because the selection of a known material based on its suitability for its intended purpose is prima facie obvious (MPEP 2144.07) and the wafer has high resistivity, increased gettering ability, and is resistant to slip dislocations.
Referring to claim 26, see remarks above regarding claim 25.
Referring to claim 28 and 30, see remarks above regarding claims 27 and 29.
Claim(s) 23, 25, 27, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Magari et al (JP 2009-38124), an English computer translation (CT) is provided in view of Murphy et al (US 2006/0267024) and Li et al (CN 108538972A), an English computer translation (CT) is provided.
Magari et al teaches a method for producing a semiconductor substrate including a silicon single crystal substrate having a front surface and a back surface; and a epitaxial semiconductor thin film formed on the front surface, the method comprising the steps of: (1) providing a silicon single crystal substrate having a front surface and a back surface; (2) implanting carbon into at least the front surface and the back surface of the silicon single crystal substrate by an RTA method to form a carbon diffusion layer having a thickness of 2 mm or less with a carbon concentration of 5E+16 atoms/cm3 or more (abstract; CT pgs 7-11 teaches a silicon single crystal substrate is implanted with carbon to form a carbon implanted layer with a carbon dose amount of 1x1014 ions/cm2 or more and performing RTA at 1175°C for 30 secs to restore crystallinity, then forming an epitaxial layer on the surface of the substrate). Overlapping ranges are prima facie obvious (MPEP 2144.05).
Magari et al teaches forming an epitaxial film on the Si substrate after forming the carbon diffusion layer (Abstract).
In a method of forming a semiconductor structure, Murphy et al teaches a silicon wafer 1 (Fig 1a), implanting carbon ion and performing a heat treatment to form a SiC layer 4 (Fig 1b-1e), and depositing an epitaxial layer 5 (Fig 1f) of GaN, AlGaN, or InAlGaN layer on the SiC layer 4b. (See Abstract; [0023]-[0046]; Fig 1).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Magari et al by depositing a gallium nitride layer, as taught by Murphy et al, to form a useful semiconductor device structure.
The combination of Magari et al and Murphy et al teaches deposition of GaN on a substrate, however does not explicitly teach vapor deposition.
In a method forming GaN films, Li et al teaches a Si substrate and preparing GaN by MOCVD on the Si substrate; depositing a pre-laid Al layer with a thickness of 1-1.5 nm at 800-980°C using trimethylaluminum (TMAl), a AlN thin film with a thickness of 100-300 nm at 900-1000°C using TMAl and ammonia; and depositing a GaN layer using trimethylgallium and ammonia at 900-1200°C (CT [0007], [0019]-[0030]). Li et al teaches growing high quality low defect density GaN which can be used for LED and other fields.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Magari et al and Murphy et al by using the method of vapor deposition of GaN on a Si substrate, as taught by Li et al, to produce a high quality low defect density GaN.
Referring to claim 25, the combination of Magari et al, Murphy et al and Li et al teaches the carbon diffusion layer has a thickness of 2 mm (Magari Abstract).
Referring to claim 27 and 29, the combination of Magari et al, Murphy et al and Li et al teaches depositing a pre-laid Al layer with a thickness of 1-1.5 nm at 800-980°C using trimethylaluminum (TMAl) (Li CT [0026]). Overlapping ranges are prima facie obvious (MPEP 2144.05)
Claim(s) 24, 26, 28 and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Magari et al (JP 2009-38124) in view of Murphy et al (US 2006/0267024) and Li et al (CN 108538972A), an English computer translation is provided, as applied to claim 23 above, and further in view of Kononchuk et al (US 2003/0106482).
The combination of Magari et al, Murphy et al and Li et al teaches all of the limitations of claim 24, as discussed above, except the silicon substrate has a resistivity of 100 ohm-cm or more, and oxygen concentration of 7E+17 atom/cm3 or less. Use of any silicon single-crystal substrate can be used regardless of a defective region of crystals, a diameter, conductivity (type and resistivity), etc for device manufacturing would have been obvious to one of ordinary skill in the art at the time of filing as evidenced by Qu, as discussed above. (See Qu [0051]).
In a method of making a high resistivity silicon wafer, Kononchuk et al teaches A high-resistivity silicon wafer comprising: a wafer substrate having a resistivity of 100 ohm-cm or greater, and an interstitial oxygen content of 8 ppma or less (abstract; [0012],Claim 23). Overlapping ranges are prima facie obvious (MPEP 2144.05). Kononchuk et al teaches the wafer has high resistivity, increased gettering ability, and is resistant to slip dislocations ([0013]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Magari et al, Murphy et al and Li et al by using a silicon substrate having a resistivity of 100 ohm-cm or more, and oxygen concentration of 7E+17 atom/cm3 or less, as taught by Kononchuk et al, because the selection of a known material based on its suitability for its intended purpose is prima facie obvious (MPEP 2144.07) and the wafer has high resistivity, increased gettering ability, and is resistant to slip dislocations.
Referring to claim 26, see remarks above regarding claim 25.
Referring to claim 28 and 30, see remarks above regarding claims 27 and 29.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi et al (US 2019/0194821) teaches the ingot or any single crystal silicon wafer sliced therefrom comprises oxygen in a concentration of no greater than about 12 PPMA (about 6×1017 atoms/cm3), such as less than about 10 PPMA (about 5×10.sup.17 atoms/cm3) ([0017]).
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MATTHEW J. SONG
Examiner
Art Unit 1714
/MATTHEW J SONG/ Primary Examiner, Art Unit 1714
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