Prosecution Insights
Last updated: August 16, 2026
Application No. 18/723,662

ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Jun 24, 2024
Priority
Dec 29, 2021 — JP 2021-215436 +1 more
Examiner
LIU, XIAOMING
Art Unit
Tech Center
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
514 granted / 596 resolved
+26.2% vs TC avg
Moderate +11% lift
Without
With
+10.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
36 currently pending
Career history
635
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
64.1%
+24.1% vs TC avg
§102
24.4%
-15.6% vs TC avg
§112
3.2%
-36.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 596 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 9/23/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-8, 10-12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chida US 2019/0392786. Re Claim 1, Chida teaches an electronic device (fig14 and 23) comprising: a first display device (255/250b, fig14 and 23, [179, 267]) and a second display device (250a, fig14 and 23, [179, 267]), wherein the first display device (255/250b, fig14 and 23, [179, 267]) comprises a first display portion (bottom layer of region 262A/B with 257, fig14A/B and 20B, [179, 245]), wherein the second display device (250a, fig14 and 23, [179, 267]) comprises a second display portion (top layer of region 262A/B with 252, fig12A, 14A/B and 20B, [165, 245]), wherein a plurality of first pixels (257, fig14A, [179]) are arranged in the first display portion, wherein a plurality of second pixels (252, fig12A and 14, [165]) are arranged in the second display portion, wherein the first display device (255/250b, fig14 and 23, [179, 267]) overlaps with the second display device (250a, fig14 and 23, [179, 267]), wherein the second display portion (top layer of region 262A/B with 252, fig12A, 14A/B and 20B, [165, 245]) is provided to surround at least part of the first display portion (bottom layer of region 262A/B with 257, fig14A/B and 20B, [179, 245]), and wherein an area occupied by each of the first pixels (257, fig14A, [179]) is smaller than an area occupied by each of the second pixels (252, fig12A and 14, [165]). Re Claim 2, Chida teaches an electronic device (fig14 and 23) comprising: a first display device (255/250b, fig14 and 23, [179, 267]) and a second display device (250a, fig14 and 23, [179, 267]), wherein the first display device (255/250b, fig14 and 23, [179, 267]) comprises a first substrate (301 or 311 used for lower level 255, fig14 and 23, [209, 260]), a first display portion (bottom layer of region 262A/B with 257, fig14A/B and 20B, [179, 245]) over the first substrate, and a second substrate (390 or 302, fig23, [264, 266]) over the first display portion, wherein the second display device (250a, fig14 and 23, [179, 267]) comprises a third substrate (311 used for upper level 250a, fig14 and 23, [209]), a second display portion (top layer of region 262A/B with 252, fig12A, 14A/B and 20B, [165, 245]) over the third substrate, and a fourth substrate (303, fig23, [270]) over the second display portion, wherein a plurality of first pixels (257, fig14A, [179]) are arranged in the first display portion, wherein a plurality of second pixels (252, fig12A and 14, [165]) are arranged in the second display portion, wherein the second substrate (390 or 302, fig23, [264, 266]) overlaps with the third substrate (311 used for upper level 250a, fig14 and 23, [209]), wherein the second substrate (390 or 302, fig23, [264, 266]), the third substrate (311 used for upper level 250a, fig14 and 23, [209]), and the fourth substrate (303, fig23, [270]) transmit light emitted from the first pixel (fig14), wherein the second display portion (top layer of region 262A/B with 252, fig12A, 14A/B and 20B, [165, 245]) is provided to surround at least part of the first display portion (bottom layer of region 262A/B with 257, fig14A/B and 20B, [179, 245]) in a plan view (fig14B2), and wherein an area occupied by each of the first pixels (257, fig14A, [179]) is smaller than an area occupied by each of the second pixels (252, fig12A and 14, [165]). Re Claim 3, Chida teaches the electronic device according to claim 2, wherein the first substrate is a semiconductor substrate (311 used for lower level 255, fig14 and 23, [209]). Re Claim 4, Chida teaches the electronic device according to claim 2, wherein a thickness of the third substrate (311 used for upper level 250a, fig14 and 23, [209]) is smaller than a thickness of the first substrate (301, 23, [260]). Re Claim 5, Chida teaches the electronic device according to claim 2, wherein the third substrate has flexibility (311 formed using a flexible material used for upper level 250a, fig14 and 23, [209]). Re Claim 6, Chida teaches the electronic device according to claim 2, wherein an adhesive layer (adhesive bond 311 to support substrate, fig23, [260]) is provided between the second substrate (302, fig23, [266]) and the third substrate (311 used for upper level 250a, fig14 and 23, [209]). Re Claim 7, Chida teaches the electronic device according to claim 1, wherein the second display portion includes a region not overlapping with the first display portion (outer peripheral region of 262A/B with 250a not overlapping 255, fig14B1 and 14B2). Re Claim 8, Chida teaches the electronic device according to claim 1, wherein the second display device (250a, fig14 and 23, [179, 267]) further comprises a third display portion (center part of upper level 250a covering region with 255 at lower level, fig14B1, 20B and 23, [245, 251]), wherein the third display portion overlaps with the first display portion (center region of 205a overlap lower region with 255, fig14B1 and 14B2), and wherein the third display portion transmits light emitted from the first pixel (fig14B2). Re Claim 10, Chida teaches the electronic device according to claim 1, wherein the first pixel comprises a first light-emitting element (370 of lower layer, fig20B and 23, [245]), wherein the second pixel comprises a second light-emitting element (370 of upper layer, fig20B and 23, [245]), wherein the first light-emitting element comprises a first pixel electrode (344a of lower layer, fig20B and 23, [242]) and a first EL layer (371 of lower layer, fig20B and 23, [245]) over the first pixel electrode, wherein the first EL layer covers an end portion of the first pixel electrode (371 covers left end of 344a, fig20B and 23), wherein the second light-emitting element comprises a second pixel electrode (344a of upper layer, fig20B and 23, [242]) and a second EL layer (371 of upper layer, fig20B and 23, [245]) over the second pixel electrode, and wherein an insulating layer (325, fig20B and 23, [242]) covering an end portion of the second pixel electrode (344a of upper layer, fig20B and 23, [242]) is provided between the second pixel electrode (344a of upper layer, fig20B and 23, [242]) and the second EL layer (371 of upper layer, fig20B and 23, [245]). Re claim 11, Chida teaches the electronic device according to claim 2, wherein the second display portion includes a region not overlapping with the first display portion (outer peripheral part of 250a not overlapping with region with 255, fig14B1 and 14B2). Re claim 12, Chida teaches the electronic device according to claim 2, wherein the second display device further comprises a third display portion (center part of 250a overlapping with 255, fig14B1), wherein the third display portion overlaps with the first display portion, and wherein the third display portion transmits light emitted from the first pixel (fig14B2). Re claim 14, Chida teaches the electronic device according to claim 2, wherein the first pixel comprises a first light-emitting element (370 of lower layer, fig20B and 23, [245]), wherein the second pixel comprises a second light-emitting element (370 of upper layer, fig20B and 23, [245]), wherein the first light-emitting element comprises a first pixel electrode (344a of lower layer, fig20B and 23, [242]) and a first EL layer (371 of lower layer, fig20B and 23, [245]) over the first pixel electrode, wherein the first EL layer covers an end portion of the first pixel electrode (371 covers left end of 344a, fig20B and 23), wherein the second light-emitting element comprises a second pixel electrode (344a of upper layer, fig20B and 23, [242]) and a second EL layer (371 of upper layer, fig20B and 23, [245]) over the second pixel electrode, and wherein an insulating layer (325, fig20B and 23, [242]) covering an end portion of the second pixel electrode (344a of upper layer, fig20B and 23, [242]) is provided between the second pixel electrode (344a of upper layer, fig20B and 23, [242]) and the second EL layer (371 of upper layer, fig20B and 23, [245]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chida US 2019/0392786 in view of Kurokawa US 2018/0096648. Re Claim 9, Chida teaches the electronic device according to claim 1, a first source driver circuit (280 connected with lower level, fig17A, [194]), and a second source driver circuit (280 connected with upper level, fig17A, [194]), wherein the first source driver circuit is electrically connected to the first pixel (fig17A), wherein the second source driver circuit is electrically connected to the second pixel (fig17A). Chida does not explicitly show wherein the electronic device further comprises a communication circuit, a control circuit wherein the communication circuit has a function of receiving is configured to receive image data, and wherein the control circuit has a function of generating is configured to generate first data representing luminance of light emitted from the first pixel and second data representing luminance of light emitted from the second pixel in accordance with the image data, and supplying to supply the first data to the first source driver circuit and the second data to the second source driver circuit. Kurokawa teaches wherein the electronic device further comprises a communication circuit (152, fig4, [87]), a control circuit (160, fig4, [88]), wherein the communication circuit has a function of receiving is configured to receive image data ([87]), and wherein the control circuit has a function of generating is configured to generate data representing luminance of light emitted from the pixel in accordance with the image data ([88]), and supplying to supply the data to the source driver circuit (180, fig4, [84]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Chida and Kurokawa to add an controller IC connected with the first and second driver circuit. The motivation to do so is to improve display, reduce power consumption and correct color tones for the display (Kurokawa, [99-101]). Re claim 13, Chida teaches the electronic device according to claim 2, a first source driver circuit (280 connected with lower level, fig17A, [194]), and a second source driver circuit (280 connected with upper level, fig17A, [194]), wherein the first source driver circuit is electrically connected to the first pixel (fig17A), wherein the second source driver circuit is electrically connected to the second pixel (fig17A). Chida does not explicitly show wherein the electronic device further comprises a communication circuit, a control circuit, wherein the communication circuit is configured to receive image data, and wherein the control circuit is configured to generate first data representing luminance of light emitted from the first pixel and second data representing luminance of light emitted from the second pixel in accordance with the image data, and to supply the first data to the first source driver circuit and the second data to the second source driver circuit. Kurokawa teaches wherein the electronic device further comprises a communication circuit (152, fig4, [87]), a control circuit (160, fig4, [88]), wherein the communication circuit has a function of receiving is configured to receive image data ([87]), and wherein the control circuit has a function of generating is configured to generate data representing luminance of light emitted from the pixel in accordance with the image data ([88]), and supplying to supply the data to the source driver circuit (180, fig4, [84]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Chida and Kurokawa to add an controller IC connected with the first and second driver circuit. The motivation to do so is to improve display, reduce power consumption and correct color tones for the display (Kurokawa, [99-101]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XIAOMING LIU/Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jun 24, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
97%
With Interview (+10.9%)
2y 2m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 596 resolved cases by this examiner. Grant probability derived from career allowance rate.

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