DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (20210210598) in view of Cheng et al. (20200266060)
Regarding Claim 1, in paragraphs 0023-0060 and particularly paragraphs 0035 and 0038 and in Figs. 1-16, Cheng ‘598 discloses a method for manufacturing a gate- all-around nanosheet structure, comprising: forming at least two channel layers 108 and at least one sacrificial layer 106, which are alternately stacked, sequentially on a substrate to form a channel stack; forming, on the substrate, a dummy gate 110 astride the channel stack; forming a first sidewall on a surface of the dummy gate; etching the at least one sacrificial layer to form a recess 114 at a side surface of the channel stack; forming a second sidewall within the recess; forming a source and a drain at two sides, respectively, of the channel stack; in response to a channel layer of the at least two channel layers being in contact with the dummy gate, , and then etching the at least one sacrificial layer to form a space for manufacturing a surrounding gate; and forming a
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required dummy gate etching in Cheng et al. ‘598 as taught by Chen et al. ‘060 in order to protect channel during the etching step.
Regarding Claim 2, in paragraphs 0053, 0054, 0073 and 0075 of Cheng ‘606 it is disclosed etching the dummy gate 132 and the channel layer 112/114 to expose the at least one sacrificial layer comprises: removing the dummy gate and the channel layer through etchingis made of a same material as the second sidewall; and etching the first dielectric film at a region above the at least one sacrificial layer, wherein the first dielectric film at a region above the second sidewall is retained.
Regarding Claim 3, in both Cheng et al. ‘598 or ‘060, etching the sacrificial layer to form the space for manufacturing the surrounding gate comprises: performing chemical etching or atomic layer etching on the sacrificial layer
Regarding Claim 4, in Cheng et al. ‘598, the at least two channel layers 108 and the at least one sacrificial layer 106, which are alternately stacked, sequentially on the substrate to form the channel stack comprises: growing at least two silicon films and at least one silicon germanium film, which are alternately stacked, sequentially on a silicon on insulator (SOI) substrate through epitaxy, wherein the at least one silicon germanium film serves as the at least one sacrificial layer, and the at least two silicon layers serve as the at least two channel layer; and performing dry etching on the channel stack to shape the channel stack into a fin extending along a first direction (see paragraph 0048)
Regarding Claim 5, in Cheng et al. ‘598, forming, on the substrate, a dummy gate 110 astride the channel stack comprises: forming a second dielectric film 112/116 on a surface of the substrate and on the channel stack; and etching the second dielectric to form the dummy gate, wherein the dummy gate and the channel stack form a stepped structure along the first direction, and the dummy gate extends across the channel stack along a second direction.
Regarding Claim 6, in Cheng et al., ‘598, wherein forming the first sidewall on the surface of the dummy gate comprises: forming a third dielectric film 126 on a surface of the dummy gate, a surface of the channel stack, and the surface of the substrate, wherein etching selectivity between the third dielectric film and the second dielectric film is not equal to 1; and etching the third dielectric film 126 to form the first sidewall, wherein a surface of the first side wall and the side surface of the channel stack are aligned with a same position along the first direction, and the first sidewall covers side surfaces of the dummy gate and a top surface of the dummy gate.
Regarding Clam 7, in Cheng et al. ‘598, wherein etching the at least one sacrificial layer to form the recess at the ide surface of the channel stack comprises: etching each sacrificial layer of the at least one sacrificial layer from a side wall of said sacrificial layer to form the recess, wherein a depth of the recess is identical to a thickness of the first sidewall (see Figs. 12 and 13)
Regarding Claim 8, in Cheng et al. ‘598, forming the second sidewall within the recess comprises: forming a first dielectric film 112/116/126 at the side surface of the channel stack, wherein a thickness of the first dielectric film is more than or equal to a depth of the recess; and etching the first dielectric film to form the second sidewall, wherein a surface of the second sidewall and a side surface of the at least two channel layers are aligned with a same position along the first direction.
Regarding Claim 9, in Cheng et al ‘598, before etching the dummy gate and the channel layer, the method further comprises: removing the third dielectric film 126 at a top of the dummy gate through planarization to expose the top surface of the dummy gate (also see paragraph 0073 of Cheng ‘060)
Regarding Claim 10, in paragraph 0054 of Cheng et al. ’060, forming the metallic surrounding gate in the space comprises: forming the metallic surrounding gate in the space through atomic layer deposition or vapor deposition.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 6/25/2026
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