Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification submitted 7/8/2024 has been accepted by the examiner.
Drawings
The drawings submitted on 7/8/2024 have been accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted up to this point have been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 recites the limitation "second gate" in the last limitation. There is insufficient antecedent basis for this limitation in the claim.
This ambiguity is inherited by its dependent claims: 13-19.
The examiner presumes this is referring to a gate of the access device.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-8, 10-13, 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Han-943 (US # 20180122943) in view of Choi-579 (US # 20170162579).
Regarding Claim 1, Han-943 teaches a semiconductor memory cell (see Fig. 3A and corresponding text) comprising:
a floating body region (24) configured to be charged to a level indicative of a state of the memory cell (502M; [0010, 13]);
a first region (16) in electrical contact with said floating body region;
a second region (18) in electrical contact with said floating body region and spaced apart from said first region (shown);
a gate (60) positioned between said first and second regions;
wherein said gate surrounds said floating body region on three sides (Fig. 8; fin embodiment 502F; [0118]);
a buried well layer (30) in electrical contact with a portion (bottom) of said floating body region; and
a substrate (10) underlying said floating body region and said first and second regions;
wherein said floating body region is configured to have at least first and second stable states ([0010, 13]);
wherein an amount of cell current from said first region to said second region when said floating body region is in said first stable state is higher than an amount of cell current from said first region to said second region when said floating body region is in said second stable state ([0010, 13] current is higher in logic-1 state than logic-0 state).
Although Han-943 discloses much of the claimed invention, it does not explicitly teach the device wherein said gate surrounds said floating body region on all sides.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Choi-579 is in the same or analogous field, and it teaches a device (see Figs. 7-8) wherein a gate (101, 102) surrounds a floating body region (channels 105a-105i) see Figs. 7-8) on all sides ([0056]).
A person having ordinary skill in the art would have recognized that modifying the gate of Han-943 with the GAA gate structure suggested by Choi-579 would be obvious. Specifically, the modification suggested by Choi-579 would be to employ a device wherein said gate surrounds said floating body region on all sides. The rationale for this obvious modification is that GAA structure provides superior electrostatic control of the floating body. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of GAA are well known in the art (see MPEP 2144.01).
Regarding Claim 2, Choi-579, as applied to claim 1, teaches the semiconductor memory cell of claim 1, wherein said floating body region comprises a nanosheet FET, a multi-bridge-channel (MBC) FET, a nanoribbon FET or a nanowire FET (channels 105a-105i are nano-wires).
Regarding Claim 4, Han-943 teaches the semiconductor memory cell of claim 1, wherein a conduction pathway for current flow through the floating body region between the first and second regions is larger when said floating body region is in said first stable state than when said floating body region is in said second stable state (logic-1 with back-bias-generated impact ionization versus logic-0).
Regarding Claim 5, Han-943 in view of Choi-579 teaches the semiconductor memory cell of claim 1, wherein a number of conduction channels for current flow through the floating body region between the first and second regions when said floating body region is in said first stable state is greater than a number of conduction channels for current flow through the floating body region between the first and second regions when said floating body region is in said second stable state (Han-943 teaches bistable conduction in logic-1 state, and Choi-579, as applied to claim 1, teaches plural nanowire channels in such a state).
Regarding Claim 6, Han-943 teaches the semiconductor memory array, including: a plurality of semiconductor memory cells as recited in claim 1, arranged in a matrix of rows and columns (see Figs. 9, array 1502).
Regarding Claim 7, Han-943 teaches a method of operating a semiconductor memory cell having a floating body region configured to be charged to a level indicative of a state of the memory cell (same mapping as claim 1);
a first region in electrical contact with said floating body region (same mapping as claim 1);
a second region in electrical contact with said floating body region and spaced apart from said first region (same mapping as claim 1);
a buried well layer in electrical contact with a portion of the floating body region (same mapping as claim 1);
a gate positioned between said first and second regions (same mapping as claim 1); and
a substrate underlying said floating body region and said first and second regions, wherein said gate surrounds said floating body region on all sides (same mapping as claim 1);
said method comprising:
operating the semiconductor memory cell with the floating body region in a first stable state (logic-1; standby and read operations [0234-238];
and operating the semiconductor memory cell with the floating body region in a second stable state (logic-2; write logic-0; see [0234-238]);
wherein an amount of cell current from the first region to the second region when the floating body region is in the first stable state is higher than an amount of cell current from the first region to the second region when the floating body region is in the second stable state (logic-1 read is higher; see [0237-238]).
Regarding Claims 8, 10, and 11, these claims are rejected for essentially the same reasons as claims 2, 4, and 5.
Regarding Claim 12, Han-943 teaches a memory cell comprising: a semiconductor memory device (see Fig. 3A) comprising:
a first floating body region (24) configured to be charged to a level indicative of a state of the memory cell (502M);
a first region (16) in electrical contact with said first floating body region;
a second region (18) in electrical contact with said first floating body region and spaced apart from said first region; and
a first gate (60) positioned between said first and second regions;
an access device (502A) comprising:
a second floating body region (24);
a third region (20) in electrical contact with said second floating body region;
a fourth region (22) is electrical contact with said second floating body region; and
a substrate (10/12) underlying said semiconductor memory device and said access device;
wherein said semiconductor memory device and said access device are electrically connected in series (18 is connected to 20); and
wherein at least one of said first gate and second gate surrounds at least one of said first floating body region and said second floating body region, respectively, on all sides (this was the combination already explained in claim 1 with the teachings of Choi-579).
Regarding Claim 13, this claim is rejected for essentially the same reasons as claim 2.
Regarding Claim 15, Han-943 teaches the memory cell of claim 12, wherein said first floating body region is configured to have at least first and second stable states;
wherein an amount of cell current from said first region to said second region when said first floating body region is in said first stable state is higher than an amount of cell current from said first region to said second region when said first floating body region is in said second stable state ([0013] the bi-stable memory transistor has higher current during logic-1 read).
Regarding Claim 16, Han-943 teaches the memory cell of claim 12, wherein said second region and said third region are a common shared region (18 and 20 are electrically connected and can be thought of as a shared n+ region).
Regarding Claim 17, Han-943 teaches the memory cell of claim 12, wherein said first floating body region comprises multiple floating channels (105a-105i) through which current can be selectively conducted between said first and second regions (conducting between source/drain).
Regarding Claim 18, Han-943 teaches the memory cell of claim 12, wherein said first gate has a first gate length and said second gate has a second gate length ([0016]);
wherein said second gate length is greater than said first gate length ([0016]) so that a lower impact ionization rate and lower gain of a parasitic bipolar are formed by said third region, second floating body region and fourth region than by said first region, first floating body region and said second region, so that charges are self-sustained in said first floating body region, but are not self-sustained said second floating body region ([0018], already explained in claim 12).
Regarding Claim 19, Han-943 teaches a semiconductor memory array, including:
a plurality of semiconductor memory cells as recited in claim 12, arranged in a matrix of rows and columns (see rejection of claim 6).
Claims 3, 9, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Han-943 (US # 20180122943) in view of Choi-579 (US # 20170162579) and further in view of Ananthan-738 (US # 20080277738).
Regarding Claim 3, although Han-943 in view of Choi-579 discloses much of the claimed invention, it does not explicitly teach the floating body region is oriented vertically.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Ananthan-738 is in the same or analogous field, and it teaches a device (see Fig. 1 and corresponding text)) wherein a floating body region (16) is oriented vertically with the WL surrounding the body (24).
A person having ordinary skill in the art would have recognized that modifying the device orientation of Han-943 in view of Choi-579 with the vertical channel suggested by Ananthan-738 would be obvious. Specifically, the modification suggested by Ananthan-738 would be to employ a device wherein the floating body region is oriented vertically. The rationale for this obvious modification is that the vertical pillar surround gate provides a smaller cell footprint and provides improved gate control with the GAA. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of vertical GAA memory cells are well known in the art (see MPEP 2144.01).
The same reasoning is applied to claims 9 and 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
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