Prosecution Insights
Last updated: August 16, 2026
Application No. 18/728,173

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Jul 11, 2024
Priority
Jan 21, 2022 — JP 2022-007959 +2 more
Examiner
LEE, WOO KYUNG
Art Unit
Tech Center
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
161 granted / 198 resolved
+21.3% vs TC avg
Strong +16% interview lift
Without
With
+15.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
37 currently pending
Career history
222
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
49.9%
+9.9% vs TC avg
§102
21.4%
-18.6% vs TC avg
§112
28.6%
-11.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 198 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2 and 5-13 are rejected under 35 U.S.C. 103 as being unpatentable over by Miyairi (US 2016/0233343) in view of Koezuka et al. (US 9,184,297; hereinafter Koezuka). Regarding claim 1, Miyairi discloses for A semiconductor device comprising that a first conductive layer (first electrode 140, Fig. 1B) over a substrate (substrate 101, Fig. 1B), a first insulating layer (first insulating layer 120, Fig. 1B) over the first conductive layer (140, Fig. 1B), the first insulating layer (120, Fig. 1B) comprising a first opening (opening in the insulating layer 120, Fig. 1B) reaching the first conductive layer (140, Fig. 1B); a second conductive layer (second electrode 150, Fig. 1B) over the first insulating layer (120, Fig. 1B), the second conductive layer (150, Fig. 1B) comprising a second opening (opening in the second electrode 150, Fig. 1B) in a region overlapping with the first opening (opening in 120, Fig. 1B); a semiconductor layer (oxide semiconductor layer 130, Fig. 1B) in the first opening and the second opening (opening in 120 and 150, Fig. 1B), the semiconductor layer (130, Fig. 1B) in contact with a top surface of the first conductive layer (top surface of 140, Fig. 1B), a side surface of the first insulating layer (side surface of 120, Fig. 1B), and a top surface and a side surface of the second conductive layer (top and side surfaces of 150, Fig. 1B), a second insulating layer (second insulating layer 160, Fig. 1B) over the semiconductor layer (130, Fig. 1B); and a third conductive layer (third electrode 170, Fig. 1B) over the second insulating layer (160, Fig. 1B), because Applicants do not specifically claim that a third conductive layer is disposed over an entirety of the second insulating layer, a portion of the third electrode 170 within an opening region by Miyairi is disposed over the second insulating 160 (Fig. 1B), wherein the first insulating layer (120, Fig. 1B) has a stacked-layer structure of a third insulating layer and a fourth insulating layer over the third insulating layer, because Miyairi further discloses that “the insulating film 120A may have a stacked-layer structure. For example, it is preferable that an oxide film formed by a sputtering method be stacked over an insulating film formed by a plasma CVD method” (emphasis added, [0127]), therefore, the oxide film formed by a sputtering method (i.e., upper portion of 120) can correspond to the claimed fourth insulating layer and the insulating film formed by a plasma CVD method (i.e., lower portion of 120) can correspond to the claimed third insulating layer. Miyairi does not explicitly disclose that the fourth insulating layer comprises a region having a higher film density than the third insulating layer. However, Koezuka disclose a thin-film transistor device including an oxide insulating film 410b, a nitride insulating film 411 disposed over the oxide insulating film 410b, and an electrode 416 disposed in an opening formed within the insulating films 410b/411 (Fig. 1B), and therefore, the oxide insulating film 410b can correspond to the claimed third insulating layer and the nitride insulating film 411 can correspond to the claimed fourth insulating layer disposed over the third insulating layer. Koezuka further discloses that “the oxide insulating film 410 is a film with low density including a void portion. The oxide insulating film 410 has a void portion (a low-density region), so that the oxide insulating film 410 as a whole has a low film density” (emphasis added, Col. 10, lines 4-7) and also discloses that “the nitride insulating film 411 has a function of covering the void portions generated in the oxide insulating film 410 due to the steps of the side end surfaces of the source electrode 408a and the drain electrode 408b. When the void portion is covered with the nitride insulating film 411, the void portion can be prevented from expanding to the outside of the oxide insulating film 410” (emphasis added, Col. 10, lines 33-39). Therefore, Koezuka teaches a stacked insulating structure in which the oxide insulating film has a relatively low film density due to the presence of void portions, while the overlying nitride insulating film functions as a denser film that seals the low-density regions and suppresses expansion of the void portions. Accordingly, one of ordinary skill in the semiconductor art would have recognized that the nitride insulating film comprises a region having relatively higher film density than the underlying oxide insulating film. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyairi to include the stacked insulating structure taught by Koezuka, including a relatively low-density oxide insulating layer and an overlying relatively higher-density nitride insulating layer, in order to improve film quality, suppress expansion of void portions, and enhance the reliability and integration of the semiconductor device. Regarding claim 2, Miyairi further discloses for a semiconductor device comprising that a first conductive layer (first electrode 140, Fig. 1B) over a substrate (substrate 101, Fig. 1B); a first insulating layer (first insulating layer 120, Fig. 1B) over the first conductive layer (140, Fig. 1B), the first insulating layer (120, Fig. 1B) comprising a first opening (opening in 120, Fig. 1B) reaching the first conductive layer; a second conductive layer (second electrode 150, Fig. 1B) over the first insulating layer (120, Fig. 1B), the second conductive layer (150, Fig. 1B) comprising a second opening (opening in 150, Fig. 1B) in a region overlapping with the first opening (opening in 120, Fig. 1B); a semiconductor layer (oxide semiconductor layer 130, Fig. 1B) in the first opening and the second opening (opening in 120/150, Fig. 1B), the semiconductor layer (130, Fig. 1B) in contact with a top surface of the first conductive layer (top surface of 140, Fig. 1B), a side surface of the first insulating layer (side surface of 120, Fig. 1B), and a top surface and a side surface of the second conductive layer (top and side surfaces of 150, Fig. 1B); a second insulating layer (second insulating layer 160, Fig. 1B) over the semiconductor layer (130, Fig. 1B); a third conductive layer (third electrode 170, Fig. 1B) over the second insulating layer (160, Fig. 1B), because Applicants do not specifically claim that a third conductive layer is disposed over an entirety of the second insulating layer, a portion of the third electrode 170 within an opening region by Miyairi is disposed over the second insulating 160 (Fig. 1B), wherein the first insulating layer (120, Fig. 1B) has a stacked-layer structure of a third insulating layer and a fourth insulating layer over the third insulating layer, because Miyairi further discloses that “the insulating film 120A may have a stacked-layer structure. For example, it is preferable that an oxide film formed by a sputtering method be stacked over an insulating film formed by a plasma CVD method” (emphasis added, [0127]), therefore, the oxide film formed by a sputtering method (i.e., upper portion of 120) can correspond to the claimed fourth insulating layer and the insulating film formed by a plasma CVD method (i.e., lower portion of 120) can correspond to the claimed third insulating layer. Miyairi does not explicitly disclose that the fourth insulating layer comprises a region containing more nitrogen than the third insulating layer. However, Koezuka discloses that “The oxide insulating film 410 can be formed using a single layer of a silicon oxide film, a silicon oxynitride film, or the like or a stacked layer thereof. Alternatively, as the oxide insulating film 410, a gallium oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like can be used” (emphasis added, Col. 8, lines 40-45) and further discloses that “the nitride insulating film 411 can be formed by a plasma CVD method or a sputtering method and using a single layer of silicon nitride, silicon nitride oxide, or the like or a stacked layer thereof” (emphasis added, Col. 8, lines 21-24), therefore, Koezuka expressly teaches a stacked insulating structure including an oxide insulating film and an overlying nitride insulating film. For example, when the oxide insulating film 410b (i.e., the claimed third insulating layer) is made of silicon oxide and the nitride insulating film 411 (i.e., the claimed fourth insulating layer) is made of silicon nitride, as disclosed by Koezuka, the overlying nitride insulating film 411 inherently contains more nitrogen than the oxide insulating film, thereby satisfying the claimed limitation, “the fourth insulating layer comprises a region containing more nitrogen than the third insulating layer”. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyairi to include the stacked insulating structure taught by Koezuka, including an oxide insulating layer and an overlying nitride insulating layer having relatively a higher nitrogen content than the underlying oxide insulating layer, in order to improve film quality, suppress expansion of void portions, and enhance the reliability and integration of the semiconductor device. Regarding claim 5, Miyairi does not explicitly disclose that a thickness of the first insulating layer is larger than or equal to 0.01 µm and smaller than 3 µm. However, Miyairi further discloses that “the channel length of the transistor 100 can be easily controlled by adjusting the thickness of the insulating layer 120 even when the transistor is miniaturized” (emphasis added, [0164]). Also, Koezuka further discloses that “as the oxide insulating film 410a, a 50-nm-thick silicon oxynitride film is formed…” (Col. 8, lines 66-67) and “the oxide insulating film was formed by stacking a 50-nm-thick first silicon oxynitride film and a 400-nm-thick second silicon oxynitride film” (Col. 39, lines 52-54), and since the oxide insulating film by Koezuka corresponds to the first insulating film in the claimed invention, a total thickness of the oxide insulating film by Koezuka could be 450 nm (or 0.45 µm), the thickness in Koezuka overlaps with the claimed thickness range. Miyairi in view of Koezuka recognizes that a thickness of the oxide insulating layer impacts the reliability and integration of the semiconductor device. The thickness of the oxide insulating layer is therefore a result-effective variable to be optimized by repeated experiments. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, a thickness of the oxide insulating layer as Miyairi in view of Moezuka has identified the thickness as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a thickness of the oxide insulating layer larger than or equal to 0.01 µm and smaller than 3 µm, in order to achieve the desired quality of insulating layer, as taught by Miyairi in view of Koezuka. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed thickness of the insulating layer). Regarding claim 6, Miyairi further discloses that the first conductive layer (140, Fig. 1B) comprises an oxide conductor, because “a conductive film 140A to be the electrode 140 is formed. As the conductive film 140A… Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used” (emphasis added, [0119]). Regarding claim 7, Miyairi further discloses that the second conductive layer (150, Fig. 1B) comprises an oxide conductor, because “the conductive films 150A and 150B can be formed using… Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.” ([0130]). Regarding claim 8, Miyairi further discloses that an end portion of the second conductive layer on the second opening side (end portion of the second electrode 150 on the opening side, Fig. 1B) is aligned or substantially aligned with an end portion of the first insulating layer on the first opening side (end portion of the first electrode 140 on the opening side, Fig. 1B). Regarding claim 9, Miyairi further discloses that an end portion of the second conductive layer on the second opening side (end portion of the second electrode 150 on the opening side, Fig. 2B) is outward from an end portion of the first insulating layer on the first opening side (end portion of the first electrode 140 on the opening side, Fig. 2B). Regarding claim 10, Miyairi discloses for a method for manufacturing a semiconductor device comprising that forming a first conductive film (conductive film 140A, Fig. 5A); processing the first conductive film (140A, Fig. 5A, [0119]) to form a first conductive layer (first electrode 140, Fig. 5C); forming a first insulating film (insulating film 120A, Fig. 5D, [0125]) over the first conductive layer (140, Fig. 5C); forming a second conductive film (conductive film 150A/150B, Fig. 5D, [0129]) over the first insulating film (120A, Fig. 5D); processing the second conductive film (150A/150B, Fig. 5D) to form a second conductive layer (second electrode 150, Fig. 7B, [0159]) comprising a first opening in a region overlapping with the first conductive layer (140, Fig. 5E); processing the first insulating film (120A, Fig. 5D) to form a first insulating layer (first insulating layer 120, Fig. 5E) comprising a second opening (opening in 120, Fig. 5E) reaching the first conductive layer (140, Fig. 5E); forming a semiconductor layer (oxide semiconductor layer 130, Fig. 7A) in contact with a top surface of the first conductive layer (top surface of 140, Fig. 7A), a side surface of the first insulating layer (side surface of 120, Fig. 7A), and a top surface and a side surface of the second conductive layer (top and side surfaces of 150, Fig. 7A); forming a second insulating layer (insulating layer 160, Fig. 7A) over the semiconductor layer (130, Fig. 7A); and forming a third conductive layer (third electrode 170, Fig. 6D) over the second insulating layer (160, Fig. 7A). Miyairi does not explicitly disclose that the first insulating layer has a stacked-layer structure of a third insulating layer and a fourth insulating layer over the third insulating layer, and wherein the fourth insulating layer comprises a region having a higher film density than the third insulating layer. However, Koezuka disclose a thin-film transistor device including an oxide insulating film 410b, a nitride insulating film 411 disposed over the oxide insulating film 410b, and an electrode 416 disposed in an opening formed within the insulating films 410b/411 (Fig. 1B), and therefore, the oxide insulating film 410b can correspond to the claimed third insulating layer and the nitride insulating film 411 can correspond to the claimed fourth insulating layer disposed over the third insulating layer. Koezuka further discloses that “the oxide insulating film 410 is a film with low density including a void portion. The oxide insulating film 410 has a void portion (a low-density region), so that the oxide insulating film 410 as a whole has a low film density” (emphasis added, Col. 10, lines 4-7) and also discloses that “the nitride insulating film 411 has a function of covering the void portions generated in the oxide insulating film 410 due to the steps of the side end surfaces of the source electrode 408a and the drain electrode 408b. When the void portion is covered with the nitride insulating film 411, the void portion can be prevented from expanding to the outside of the oxide insulating film 410” (emphasis added, Col. 10, lines 33-39). Therefore, Koezuka teaches a stacked insulating structure in which the oxide insulating film has a relatively low film density due to the presence of void portions, while the overlying nitride insulating film functions as a denser film that seals the low-density regions and suppresses expansion of the void portions. Accordingly, one of ordinary skill in the semiconductor art would have recognized that the nitride insulating film comprises a region having relatively higher film density than the underlying oxide insulating film. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyairi to include the stacked insulating structure taught by Koezuka, including a relatively low-density oxide insulating layer and an overlying relatively higher-density nitride insulating layer, in order to improve film quality, suppress expansion of void portions, and enhance the reliability and integration of the semiconductor device. Regarding claim 11, Koezuka further discloses that the fourth insulating layer (411, Fig. 1B) comprises a region containing more nitrogen than the third insulating layer (410, Fig. 1B), because Koezuka discloses that “The oxide insulating film 410 can be formed using a single layer of a silicon oxide film, a silicon oxynitride film, or the like or a stacked layer thereof. Alternatively, as the oxide insulating film 410, a gallium oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like can be used” (emphasis added, Col. 8, lines 40-45) and further discloses that “the nitride insulating film 411 can be formed by a plasma CVD method or a sputtering method and using a single layer of silicon nitride, silicon nitride oxide, or the like or a stacked layer thereof” (emphasis added, Col. 8, lines 21-24), therefore, Koezuka expressly teaches a stacked insulating structure including an oxide insulating film and an overlying nitride insulating film. For example, when the oxide insulating film 410b (i.e., the claimed third insulating layer) is made of silicon oxide and the nitride insulating film 411 (i.e., the claimed fourth insulating layer) is made of silicon nitride, as disclosed by Koezuka, the overlying nitride insulating film 411 inherently contains more nitrogen than the oxide insulating film, thereby satisfying the claimed limitation, “the fourth insulating layer comprises a region containing more nitrogen than the third insulating layer”. Regarding claim 12, Miyairi further discloses for a method for manufacturing a semiconductor device comprising that forming a first conductive film (conductive film 140A, Fig. 5A); processing the first conductive film (150A, Fig. 5A, [0119]) to form a first conductive layer (first electrode 140, Fig. 5C); forming a first insulating film (a lower portion of insulating film 120A, Fig. 5D, [0125]) over the first conductive layer (first electrode 140, Fig. 5C), because Miyairi further discloses that “the insulating film 120A may have a stacked-layer structure. For example, it is preferable that an oxide film formed by a sputtering method be stacked over an insulating film formed by a plasma CVD method” (emphasis added, [0127]), therefore, the oxide film by a sputtering method (i.e., upper portion of 120A) can correspond to the claimed second insulating film and the insulating film by a plasma CVD method (i.e., lower portion of 120A) can correspond to the claimed first insulating film; forming a metal oxide layer (conductive film 150A, Fig. 5D) over the first insulating film (120A, Fig. 5D) to supply oxygen to the first insulating film (120A, Fig. 5D), because “the conductive films 150A and 150B can be formed using… Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.” ([0130]); removing the metal oxide layer (removing a center portion of 150A to form an opening, Fig. 5E); forming a second insulating film (a upper portion of 120A, Fig. 5D) over the first insulating film (a lower portion of 120A, Fig. 5D), because Miyairi further discloses that “the insulating film 120A may have a stacked-layer structure. For example, it is preferable that an oxide film formed by a sputtering method be stacked over an insulating film formed by a plasma CVD method” (emphasis added, [0127]), therefore, the oxide film by a sputtering method (i.e., upper portion of 120A) can correspond to the claimed second insulating film and the insulating film by a plasma CVD method (i.e., lower portion of 120A) can correspond to the claimed first insulating film; forming a second conductive film (conductive film 150B, Fig. 5D, [0129]) over the second insulating film (upper portion of 120A, Fig. 5D); processing the second conductive film (150B, Fig. 5E) to form a second conductive layer (second electrode 150, Fig. 7B) comprising a first opening in a region (opening in 150, Fig. 7B) overlapping with the first conductive layer (140, Fig. 1B); processing the first insulating film (upper portion of 120A, Fig. 5E, [0127]) and the second insulating film (lower portion of 120A, Fig. 5E, [0127]) to form a first insulating layer (lower portion of the stacked-layer structure 120, [0127]) and a second insulating layer (upper portion of the stacked-layer structure 120, [0127]) each of which comprises a second opening (opening in 120, Fig. 5E) reaching the first conductive layer (140, Fig. 5E); forming a semiconductor layer (oxide semiconductor layer 130, Fig. 7A) in contact with a top surface of the first conductive layer (top surface of 140, Fig. 7A), a side surface of the first insulating layer (side surface of the lower portion of 120, Fig. 7A, [0127]), a side surface of the second insulating layer (side surface of the upper portion of 120, Fig. 7A, [0127]), and a top surface and a side surface of the second conductive layer (top and side surfaces of 150, Fig. 7A); forming a third insulating layer (insulating layer 125, Fig. 7C) over the semiconductor layer (130, Fig. 7C); and forming a third conductive layer (third electrode 170, Fig. 1B) over the third insulating layer (125, Fig. 1B). Miyairi does not explicitly disclose that the second insulating layer comprises a region having a higher film density than the first insulating layer. However, Koezuka disclose a thin-film transistor device including an oxide insulating film 410b, a nitride insulating film 411 disposed over the oxide insulating film 410b, and an electrode 416 disposed in an opening formed within the insulating films 410b/411 (Fig. 1B), and therefore, the oxide insulating film 410b can correspond to the claimed first insulating layer and the nitride insulating film 411 can correspond to the claimed second insulating layer disposed over the third insulating layer. Koezuka further discloses that “the oxide insulating film 410 is a film with low density including a void portion. The oxide insulating film 410 has a void portion (a low-density region), so that the oxide insulating film 410 as a whole has a low film density” (emphasis added, Col. 10, lines 4-7) and also discloses that “the nitride insulating film 411 has a function of covering the void portions generated in the oxide insulating film 410 due to the steps of the side end surfaces of the source electrode 408a and the drain electrode 408b. When the void portion is covered with the nitride insulating film 411, the void portion can be prevented from expanding to the outside of the oxide insulating film 410” (emphasis added, Col. 10, lines 33-39). Therefore, Koezuka teaches a stacked insulating structure in which the oxide insulating film has a relatively low film density due to the presence of void portions, while the overlying nitride insulating film functions as a denser film that seals the low-density regions and suppresses expansion of the void portions. Accordingly, one of ordinary skill in the semiconductor art would have recognized that the nitride insulating film comprises a region having relatively higher film density than the underlying oxide insulating film. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Miyairi to include the stacked insulating structure taught by Koezuka, including a relatively low-density oxide insulating layer and an overlying relatively higher-density nitride insulating layer, in order to improve film quality, suppress expansion of void portions, and enhance the reliability and integration of the semiconductor device. Regarding claim 13, Koezuka further discloses that the second insulating layer (nitride insulating layer 411, Fig. 1B) comprises a region containing more nitrogen than the first insulating layer (oxide insulating layer 410, Fig. 1B), because Koezuka discloses that “The oxide insulating film 410 can be formed using a single layer of a silicon oxide film, a silicon oxynitride film, or the like or a stacked layer thereof. Alternatively, as the oxide insulating film 410, a gallium oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like can be used” (emphasis added, Col. 8, lines 40-45) and further discloses that “the nitride insulating film 411 can be formed by a plasma CVD method or a sputtering method and using a single layer of silicon nitride, silicon nitride oxide, or the like or a stacked layer thereof” (emphasis added, Col. 8, lines 21-24), therefore, Koezuka expressly teaches a stacked insulating structure including an oxide insulating film and an overlying nitride insulating film. For example, when the oxide insulating film 410b (i.e., the claimed first insulating layer) is made of silicon oxide and the nitride insulating film 411 (i.e., the claimed second insulating layer) is made of silicon nitride, as disclosed by Koezuka, the overlying nitride insulating film 411 inherently contains more nitrogen than the oxide insulating film, thereby satisfying the claimed limitation, “the fourth insulating layer comprises a region containing more nitrogen than the third insulating layer”. Allowable Subject Matter Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior arts cited in this Office Action do not teach the claimed limitations, “the fifth insulating layer comprises a region having a higher film density than the third insulating layer” of claim 3 and “the fifth insulating layer comprises a region containing more nitrogen than the third insulating layer” of claim 4. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /WOO K LEE/Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Jul 11, 2024
Application Filed
Jul 30, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707686
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
3y 4m to grant Granted Aug 11, 2026
Patent 12707713
STACKED DEVICE STRUCTURES AND METHODS FOR FORMING THE SAME
2y 1m to grant Granted Aug 11, 2026
Patent 12698442
ELECTROLUMINESCENT DEVICE AND SEMICONDUCTOR NANOPARTICLE
3y 11m to grant Granted Aug 04, 2026
Patent 12701910
Flexible Display Apparatus
2y 7m to grant Granted Aug 04, 2026
Patent 12690212
SEMICONDUCTOR OPTOELECTRONIC INTEGRATED CIRCUIT AND METHODOLOGY FOR MAKING SAME EMPLOYING GATE-ALL-AROUND EPITAXIAL STRUCTURES
3y 4m to grant Granted Jul 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
97%
With Interview (+15.9%)
3y 2m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 198 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month