Prosecution Insights
Last updated: October 02, 2026
Application No. 18/729,041

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE

Non-Final OA §112
Filed
Jul 15, 2024
Priority
Feb 02, 2022 — JP 2022-015094 +1 more
Examiner
JEAN BAPTISTE, WILNER
Art Unit
Tech Center
Assignee
RESONAC Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
956 granted / 1104 resolved
+26.6% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
22 currently pending
Career history
1119
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
62.4%
+22.4% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1104 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings 2. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a circuit” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 3. The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL. The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 4. Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites “a semiconductor package comprising an organic substrate having a circuit, a semiconductor chip that is mounted on a part of one surface of the organic substrate and is electrically connected to the circuit”. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to practice the invention commensurate in scope with these claims. Specifically, “an organic substrate having a circuit”. For example, [0051] indicates “organic substrate 1 having a circuit (which may be hereinafter referred simply to as an “organic substrate 1”) is a substrate”. As such, the applicant's specification does not disclose enough to enable one of ordinary skill in the art to determine the difference between the substrate and the circuit. 5. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites “an organic substrate having a circuit”, in line 2. It is not clear if the Applicant is trying to further limit “the substrate” from line 2 or introduce a different “substrate as a circuit”. For the purposes of examination Examiner will treat “substrate" as being different from “circuit". Allowable Subject Matter 6. Claims 1-13 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Remarks: 7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chiu et al., US-9,018,648-B2, describing a package structure for light-emitting diodes (LEDs). The package structure includes a substrate, a heat-dissipating structure disposed on the substrate, and a plurality of LED chips uniformly disposed on the heat-dissipating structure. The heat-dissipating structure has a central portion and at least one peripheral portion surrounding thereof. The central portion is capable-of-dissipating more heat than the peripheral portion. Thus, the temperature difference between the LED chips disposed on the central portion and the LED chips disposed on the peripheral portion can be reduced (see abstract, fig. 1c). TOBA et al., US-20240306308-A1 (hereinafter “Toba”) discloses a semiconductor package includes a wiring board and a semiconductor element mounted on the wiring board. The wiring board includes a first insulating material layer having a surface with an arithmetic average roughness Ra of 100 nm or less, a metal wiring provided on the surface of the first insulating material layer, and a second insulating material layer provided to cover the metal wiring. The metal wiring is configured by a metal layer in contact with the surface of the first insulating material layer and a conductive part stacked on a surface of the metal layer, and a nickel content rate of the metal layer is 0.25 to 20% by mass (see abstract, fig. 3). 8. Prior arts such as Chiu et al., and Toba et al., made available do not teach, or fairly suggest, a semiconductor package comprising an organic substrate having a circuit, a semiconductor chip that is mounted on a part of one surface of the organic substrate, and is electrically connected to the circuit, and a metal plate that is adhered to the one surface of the organic substrate in at least a part of a region where the semiconductor chip is not mounted, and is not electrically connected to the circuit, a metal constituting the metal plate having an average thermal expansion coefficient at 30 to 2600C of 3 to 15 ppm/C, as in claim 1. Hence the best prior art of record fails to teach the invention as set forth in claims 1-13 and the examiner can find no teaching of the specific invention, nor reasons within the cited prior art or on her own to combine the elements of these references other than the applicant’s own reasoning to fully encompass the current pending claims. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jul 15, 2024
Application Filed
Sep 02, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751341
SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHODS FOR ALIGNING DIES USING REGISTRATION MARKS
2y 6m to grant Granted Sep 29, 2026
Patent 12745404
SEMICONDUCTOR MEMORY DEVICE
3y 0m to grant Granted Sep 22, 2026
Patent 12745474
PHOTOELECTRIC CONVERSION APPARATUS AND EQUIPMENT
2y 6m to grant Granted Sep 22, 2026
Patent 12733481
DEVICE HAVING DIFFERENT FIRST METALLIZATION LAYER AND FIRST BURIED METALLIZATION LAYER ARCHITECTURES AND METHOD OF MANUFACTURING SAME
2y 8m to grant Granted Sep 08, 2026
Patent 12721223
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
3y 4m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+5.1%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1104 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month