DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/19/2024, 11/13/2025, 2/9/2026 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Izumi (US 2016/0064281).
Regarding claim 15, Izumi discloses, in at least figures 12-15 and related text, a non-volatile memory device, comprising:
a plurality of alternating layers (32/46, [83], [85]), wherein the plurality of alternating layers (32/46, [83], [85]) comprise:
a plurality of stacked layer pairs (pairs of 32/46, [83], [85]) that each comprise a first layer (46, [85]) that comprises a first material and a second layer (32, [83]) that comprises a second material which is different from the first material, wherein the plurality of stacked layer pairs (pairs of 32/46, [83], [85]) are stacked in a first direction (vertical direction, figures) and comprise N stacked layer pairs, and N is greater than 10 ([28]); and
a plurality of conductive columns (66, [86]), wherein each of the conductive columns (66, [86]) are aligned in a first pitch direction (horizontal direction, figures), and are separated in the first pitch direction (horizontal direction, figures) by a pitch length, N-1 of the conductive columns (66, [86]) extend through one or more stacked layer pairs (pairs of 32/46, [83], [85]), and each of the conductive columns (66, [86]) comprises a dielectric layer (64, [78]) that is disposed between a conductive material disposed within the conductive column (66, [86]) and the layers of the one or more stacked layer pairs (pairs of 32/46, [83], [85]) that the conductive column (66, [86]) extends through,
wherein a voltage is applied to the conductive material of the conductive column during operation of the non- volatile memory device (the limitation of "a voltage is applied to the conductive material of the conductive column during operation of the non- volatile memory device" has not patentable weight because it is interpreted as intended use),
wherein the first material (material of 46, [85]) and the conductive material (material of 66, [85], [86]) each essentially comprise the same material ([85]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Izumi (US 2016/0064281) in view of Suda (US 2021/0343539).
Regarding claim 1, Izumi discloses, in at least figures 1-6 and related text, a method of forming a non-volatile memory device, comprising:
etching a plurality of alternating layers (32/42, [22]) formed over a surface of a substrate (8, [17]), wherein the alternating layers comprises a first layer (32 or 42, [22]) and a second layer (32 or 42, [22]) that are stacked in a vertical direction,
wherein the substrate comprises:
a hard mask layer (36, [44]) disposed over the first layer (32 or 42, [22]) and the second layer (32 or 42, [22]) of the plurality of alternating layers (32/42, [22]), wherein the first layer (32 or 42, [22]) comprises a first material ([24], [25]) and the second layer (32 or 42, [22]) comprises a second material ([24], [25]) that is different from the first material ([24], [25]);
an array of mask openings (59, [47]) formed in the hard mask layer (36, [44]) that are aligned in a first pitch direction (horizontal direction, figures), and have a pitch length in the first pitch direction (horizontal direction, figures) between adjacent mask openings in the array of mask openings (59, [47]); and
a first photoresist layer (47, [52]) disposed over the hard mask layer (36, [44]) and over two or more of the mask openings (59, [47]) in the array of openings (59, [47]), wherein at least one of the mask openings (59, [47]) in the array of openings (59, [47]) is exposed to an opening (69, [58]) formed in the first photoresist layer (47, [52]),
wherein the processing causes
the opening (69, [58]) formed in the first photoresist layer (47, [52]) to increase in size in the first pitch direction (horizontal direction, figures) a length that equal to the pitch length during a first time interval (interval between cycles of 69, [58]), and
simultaneously etch through a thickness of the first layer (32 or 42, [22]) and the second layer (32 or 42, [22]) during the first time interval (interval between cycles of 69, [58]).
Izumi does not explicitly disclose etching the plurality of layers comprises: (a) delivering a processing gas composition to a processing region of a process chamber; (b) forming a plasma in the processing region of the process chamber, wherein the plasma comprises the processing gas composition; (c) establishing a voltage waveform at an electrode that is positioned a distance from a substrate supporting surface of a substrate support that is disposed within a processing region of a processing chamber while the plasma is formed over a substrate that is positioned on the substrate supporting surface.
Suda teaches, in at least figures 1-4 and related text, the method comprising etching the plurality of layers comprises: (a) delivering a processing gas composition ([22]-[25], [36]) to a processing region (10s, [55]) of a process chamber (10, [55]); (b) forming a plasma in the processing region (10s, [55]) of the process chamber (10, [55]), wherein the plasma comprises the processing gas composition ([36]); (c) establishing a voltage waveform (62/64, [69]) at an electrode (18, [58]) that is positioned a distance from a substrate supporting surface of a substrate support (14, [57]) that is disposed within a processing region (10s, [55]) of a process chamber (10, [55]) while the plasma is formed over a substrate (W, [56]) that is positioned on the substrate supporting surface (surface of 14, [57]), for the purpose of improving selectivity in etching of a silicon-containing film over etching of a mask in plasma etching ([5]).
Izumi and Suda are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Izumi with the specified features of Suda because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Izumi to have the etching the plurality of layers comprising: (a) delivering a processing gas composition to a processing region of a process chamber; (b) forming a plasma in the processing region of the process chamber, wherein the plasma comprises the processing gas composition; (c) establishing a voltage waveform at an electrode that is positioned a distance from a substrate supporting surface of a substrate support that is disposed within a processing region of a processing chamber while the plasma is formed over a substrate that is positioned on the substrate supporting surface, as taught by Suda, for the purpose of improving selectivity in etching of a silicon-containing film over etching of a mask in plasma etching ([5], Suda).
Regarding claim 2, Izumi in view of Suda discloses the method of claim 1 as described above.
Izumi further discloses, in at least figures 1-6 and related text, the first material ([24], [25]) comprises silicon and nitrogen, and the second material ([24], [25]) comprises silicon and oxygen.
Regarding claim 3, Izumi in view of Suda discloses the method of claim 1 as described above.
Izumi further discloses, in at least figures 1-6 and related text, the first material ([24], [25]) comprises silicon and nitrogen, and the second material ([24], [25]) comprises polysilicon.
Regarding claim 6, Izumi in view of Suda discloses the method of claim 1 as described above.
Suda further teaches, in at least figures 1-4 and related text, the processing gas composition ([81]) comprises at least one of C4F6, C3F6, CF4, NF3, C3F8, C4F8, CH3F, CH2F2, SF6, SiF4, and WF6, and at least one of HBr, He, Ar, Xe, N2, Kr, and O2 ([82]), for the purpose of improving selectivity in etching of a silicon-containing film over etching of a mask in plasma etching ([5]).
Regarding claim 7, Izumi in view of Suda discloses the method of claim 1 as described above.
Izumi further discloses, in at least figures 1-6 and related text, the alternating layers (32/42, [22]) comprise a plurality of the first layers (32, [22]) and the second layers (42, [22]) that are alternately stacked in a vertical direction, and the method further comprises performing (a), (b) and (c) until
the first photoresist layer (47, [52]) positioned over the two or more mask openings in the array of mask openings (59, [47]) is removed, and
patterned openings (69, [58]) formed in the alternating layers (32/42, [22]) through each of the mask openings (59, [47]) have a bottom surface that has a differing depth within the alternating layers (32/42, [22]), wherein the bottom surface of each of the patterned openings (69, [58]) have a first end that is contact with a portion of a first layer of the plurality of the second layers (42, [22]) (figures).
Regarding claim 8, Izumi in view of Suda discloses the method of claim 7 as described above.
Izumi further discloses, in at least figures 1-6, 9-10, and related text, depositing a dielectric layer (64L, [77]) over the surfaces of the patterned openings (69, [58]) formed in the alternating layers (32/42, [22]), and
removing at least a portion of the deposited dielectric layer (64L, [77]) from the bottom surface of each of the patterned openings (69, [58]) formed in the alternating layers (32/42, [22]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Izumi (US 2016/0064281) in view of Suda (US 2021/0343539), and further in view of Ando (US 2021/0391536).
Regarding claim 4, Izumi in view of Suda discloses the method of claim 1 as described above.
Izumi in view of Suda does not explicitly disclose the first photoresist layer comprises a DNQ- Novolac photoresist, an epoxy-based polymer, or an off-stoichiometry thiol-enes (OSTE) polymer.
Ando teaches, in at least figure 6 and related text, the method comprising the first photoresist layer (502, [51]) comprises a DNQ- Novolac photoresist, an epoxy-based polymer ([51]), or an off-stoichiometry thiol-enes (OSTE) polymer, for the purpose of providing OPLs used as etch masks for pattern transfers into inorganic substrates, to fill pre-existing features, and to planarize the substrate to allow for larger patterning process windows ([50]).
Izumi, Suda, and Ando are analogous art because they all are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Izumi in view of Suda with the specified features of Ando because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Izumi in view of Suda to have the first photoresist layer comprising a DNQ- Novolac photoresist, an epoxy-based polymer, or an off-stoichiometry thiol-enes (OSTE) polymer, as taught by Ando, for the purpose of providing OPLs used as etch masks for pattern transfers into inorganic substrates, to fill pre-existing features, and to planarize the substrate to allow for larger patterning process windows ([50], Ando).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Izumi (US 2016/0064281) in view of Suda (US 2021/0343539), and further in view of Gellineau (US 2018/0350699).
Regarding claim 11, Izumi in view of Suda discloses the method of claim 1 as described above.
Izumi in view of Suda does not explicitly disclose receiving, by a controller, a signal from a sensor that is positioned to detect a property of a surface of the substrate while etching the plurality of layers, wherein the signal includes information regarding the detected property of the substrate surface; determining, by the controller, that one or more characteristics of a plasma etching process needs to be adjusted based on the received signal.
Gellineau teaches, in at least figure 13 and related text, the method comprising receiving, by a controller (230/209, [112], [113]), a signal (235, [111]) from a sensor (219, [111]) that is positioned to detect a property of a surface of the substrate (201, [105], [107]) while etching the plurality of layers, wherein the signal (235, [111]) includes information regarding the detected property of the substrate surface (201, [105], [107]); determining, by the controller (230/209, [112], [113]), that one or more characteristics of a plasma etching process needs to be adjusted based on the received signal (235, [111]) ([113]), for the purpose of providing yield improvement of an on-going semiconductor fabrication process flow ([19]).
Izumi, Suda, and Gellineau are analogous art because they all are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Izumi in view of Suda with the specified features of Gellineau because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Izumi in view of Suda to have the receiving, by a controller, a signal from a sensor that is positioned to detect a property of a surface of the substrate while etching the plurality of layers, wherein the signal includes information regarding the detected property of the substrate surface; the determining, by the controller, that one or more characteristics of a plasma etching process needs to be adjusted based on the received signal, as taught by Gellineau, for the purpose of providing yield improvement of an on-going semiconductor fabrication process flow ([19], Gellineau).
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Izumi (US 2016/0064281) in view of Suda (US 2021/0343539), and further in view of Hu (US 2017/0278864).
Regarding claim 12, Izumi discloses, in at least figures 1-6 and related text, a method of forming a non-volatile memory device, comprising:
the substrate comprises:
a hard mask layer (36, [44]) disposed over a plurality of alternating layers (32/42, [22]) formed over a surface of the substrate (8, [17]), wherein the alternating layers (32/42, [22]) comprises a first layer (32, [22]) and a second layer (42, [22]) that are stacked in a vertical direction;
an array of mask openings (59, [47]) formed in the hard mask layer (36, [44]) that are aligned in a first pitch direction (horizontal direction, figures), and have a pitch length in the first pitch direction (horizontal direction, figures) between adjacent mask openings in the array of openings (59, [47]); and
a first photoresist layer (47, [52]) disposed over the hard mask layer (36, [44]) and over two or more of the mask openings in the array of mask openings (59, [47]), and comprises an opening (69, [58]) in the first photoresist layer (47, [52]) that has an exposed surface, wherein the opening (69, [58]) is positioned to expose a first mask opening of the array of mask openings (59, [47]) or expose a portion of the hard mask layer adjacent to the first mask opening of the array of mask openings (59, [47]);
etching a plurality of alternating layers (32/42, [22]) formed over the surface of a substrate (8, [17]), wherein etching the plurality of layers (32/42, [22]) comprises: etching the plurality of alternating layers(32/42, [22]) causes the first photoresist layer (47, [52]) to be etched so that each of the mask openings in the array of mask openings (59, [47]) are serially exposed, and causes portions of the alternating layers (32/42, [22]) disposed below the serially exposed mask openings (59, [47]) to form patterned openings (69, [58]) that each have a differing depth within the alternating layers (32/42, [22]).
Izumi does not explicitly disclose positioning a substrate on a surface of a substrate support that is disposed within a processing region of a processing chamber; delivering a processing gas composition to the processing region of the process chamber; delivering a processing gas composition to the processing region of the process chamber; forming a plasma in the processing region of the process chamber, wherein the plasma comprise the processing gas composition and the plasma is formed over the first photoresist layer and the opening formed therein; each of the mask openings in the array of mask openings are serially exposed to the formed plasma during the process of etching the plurality of alternating layers.
Suda teaches, in at least figures 1-4 and related text, the method comprising a substrate (W, [56]) on a surface of a substrate support (14, [57]) that is disposed within a processing region (10s, [55]) of a process chamber (10, [55]); delivering a processing gas composition ([22]-[25], [36]) to the processing region (10s, [55]) of the process chamber (10, [55]); delivering a processing gas composition ([22]-[25], [36]) to the processing region (10s, [55]) of the process chamber (10, [55]); forming a plasma in the processing region (10s, [55]) of the process chamber (10, [55]), wherein the plasma comprise the processing gas composition ([36]), for the purpose of improving selectivity in etching of a silicon-containing film over etching of a mask in plasma etching ([5]).
Hu teaches, in at least figures 10-16 and related text, the method comprising the plasma is formed over the first photoresist layer (203, [64]) and the opening (opening of 203, figures) formed therein; each of the mask openings in the array of mask openings (206a-206e, [57]) are serially exposed to the formed plasma during the process of etching the plurality of alternating layers (201a/202a…201d/201e, [41]), for the purpose of reducing etching damages to certain structures of the 3D NAND device ([8]).
Izumi, Suda, and Hu are analogous art because they all are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Izumi with the specified features of Suda and Hu because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Izumi to have the positioning a substrate on a surface of a substrate support that is disposed within a processing region of a processing chamber; the delivering a processing gas composition to the processing region of the process chamber; the delivering a processing gas composition to the processing region of the process chamber; the forming a plasma in the processing region of the process chamber, as taught by Suda and the plasma being formed over the first photoresist layer and the opening formed therein; each of the mask openings in the array of mask openings being serially exposed to the formed plasma during the process of etching the plurality of alternating layers, as taught by Hu, for the purpose of improving selectivity in etching of a silicon-containing film over etching of a mask in plasma etching ([5], Suda) and reducing etching damages to certain structures of the 3D NAND device ([8], Hu).
Regarding claim 13, Izumi in view of Suda and Hu discloses the method of claim 12 as described above.
Izumi further discloses, in at least figures 1-6 and related text, a bottom surface of each of the patterned openings (69, [58]) have a first end that is contact with a portion of a first layer of the plurality of the second layers (42, [22]).
Regarding claim 14, Izumi in view of Suda and Hu discloses the method of claim 12 as described above.
Suda further teaches, in at least figures 1-4 and related text, establishing a voltage waveform (62/64, [69]) at an electrode (18, [58]) that is positioned a distance from the substrate supporting surface (surface of 14, [57]), for the purpose of improving selectivity in etching of a silicon-containing film over etching of a mask in plasma etching ([5]).
Hu further teaches, in at least figures 10-16 and related text, the plasma is formed over the first photoresist layer (203, [64]) and the opening (opening of 203, figures) formed therein, for the purpose of reducing etching damages to certain structures of the 3D NAND device ([8]).
Response to Amendment
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 5 that recite "a series of pulses that each have a first time interval that extends for 200 ns to 400 ns, and a second time interval accounts for at least 80% of each pulse cycle of the series of pulses, and each pulse in the series of pulses has a peak-to-peak voltage that is between about 2 kV and 20 kV" in combination with other elements of the base claims 1 and 5.
Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 7, 8, and 9 that recite "filling the patterned openings formed in the alternating layers with the first material" in combination with other elements of the base claims 1, 7, 8, and 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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