DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 2, 2026, has been entered.
Claims 1-2, 4-11, and 13-21 are pending in this office action and presented for examination. Claims 1, 10, and 19 are newly amended, and claim 21 is newly added by the RCE received March 16, 2025.
Specification
The title of the invention is not descriptive. Examiner submits that the concept of loads and stores of unaligned data structures that span across data chunks was well-known before the effective filing date of the claimed invention. Similarly, Examiner submits that loading to, or storing from, a “register” was widespread before the effective filing date of the claimed invention, and further submits that it is unclear as to the difference, in the context of the title, between loading and storing in a register, and unclear as to whether “in a register” is intended to further modify “load”. As such, the title does not have sufficient informative value in indexing, classifying, searching, etc. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 recites the limitation “the length of the register” in line 1. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0024]) does not appear to provide support for a length of a register.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4-11, and 13-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “lengths of each of the two data chunks” in lines 10-11. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether the aforementioned lengths are the same as, or different from, “a length of each of the at least two data chunks” in claim 1, lines 7-8. For example, it is unclear whether each data chunk is recited as having plural lengths. For example, “the two data chunks” has insufficient antecedent basis in the claims. Note that the limitation “the lengths of each of the two data chunks” is recited in claim 21, line 2.
Claims 2, 4-9, and 21 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 10 recites the limitation “lengths of each of the two data chunks” in lines 10-11. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether the aforementioned lengths are the same as, or different from, “a length of each of the at least two data chunks” in claim 10, lines 7-8. For example, it is unclear whether each data chunk is recited as having plural lengths. For example, “the two data chunks” has insufficient antecedent basis in the claims.
Claims 11 and 13-18 are rejected for failing to alleviate the rejection of claim 10 above.
Claim 19 recites the limitation “lengths of each of the two data chunks” in lines 8-9. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether the aforementioned lengths are the same as, or different from, “a length of each of the at least two data chunks” in claim 19, lines 5-6. For example, it is unclear whether each data chunk is recited as having plural lengths. For example, “the two data chunks” has insufficient antecedent basis in the claims.
Claim 20 is rejected for failing to alleviate the rejection of claim 19 above.
Claim 21 recites the limitation “the length of the register” in line 1. However, there is insufficient antecedent basis for this limitation in the claims. It is further indefinite as to whether a length of a register is the same as, or different from, a width of a register, as conveyed via the limitation “a register that has a width” in claim 1, lines 9-10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 9-11, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di (US 20180300134 A1) in view of Hammarlund et al. (Hammarlund) (US 20070156990 A1) in view of Roussel et al. (Roussel) (US 20030120889 A1).
Consider claim 1, Di discloses a processor ([0017], line 2, processor 100), comprising: a memory configured to store unaligned data structures ([0024], lines 1-5, if instead the load is a cache line unaligned load instruction, then the MOB 114 begins processing the load in a similar manner in which it uses the physical address, once determined, to access a portion of the data from a first cache line stored in the cache memory 116; [0023], lines 5-8, the MOB 114 uses the physical address to access the data from a cache line stored in the cache memory 116 (which may ultimately be retrieved from the system memory 118)); a load unit comprising circuitry ([0020], lines 20-22, the term “MOB” is a common lexicon for a memory execution unit that executes memory type instructions, including load and store instructions; [0025], lines 1-3, the MOB 114 incorporates reload circuitry 124 that performs additional functions in the event that the load is a cache line unaligned load instruction; [0027], lines 23-24, it is noted that the reload circuitry 124, the memory 128 and the merge unit 130 may all be incorporated within the MOB 114 and may be considered as part of the MOB 114) configured to: receive at least two data chunks from the memory using respective read cycles ([0024], lines 1-5, if instead the load is a cache line unaligned load instruction, then the MOB 114 begins processing the load in a similar manner in which it uses the physical address, once determined, to access a portion of the data from a first cache line stored in the cache memory 116; [0025], lines 28-33, the scheduler 112 is temporarily stalled for one cycle, and the same load instruction with the incremented address and the same data length is dispatched as the very next instruction just behind the original cache line unaligned load instruction), identify an unaligned data structure within the at least two data chunks ([0022], lines 1-4, the MOB 114 receives load instructions and determines whether the load is cache line aligned or unaligned. Each load instruction includes a specified address and a specified data length; [0024], lines 7-12, the specified address points to a location within the current cache line and the data length otherwise extends beyond the current cache line to the next sequential cache line. Thus, the current cache line includes only a portion of the target data so that the cache line unaligned load instruction returns only a partial result), wherein the unaligned data structure has a length that is greater than a length of each of the at least two data chunks ([0004], lines 15-16, alternative cache line sizes are contemplated; [0029], line 10, the specified data length is DL), and store the unaligned data structure in a register ([0021], lines 14-16, a load instruction, for example, retrieves data from the cache memory 116 and temporarily stores the data into the allocated register in the PRF; [0027], lines 20-23, the MOB 114 or the merge unit 130 then provides the merged result data via path 122 for storage in the ROB 120 or in the allocated register of the PRF (and forwarding, if applicable)), wherein the unaligned data structure spans across the at least two data chunks and does not align with the at least two data chunks ([0024], lines 1-2, cache line unaligned load instruction; [0024], lines 7-12, the specified address points to a location within the current cache line and the data length otherwise extends beyond the current cache line to the next sequential cache line. Thus, the current cache line includes only a portion of the target data so that the cache line unaligned load instruction returns only a partial result); and data processing circuitry in a core of the processor configured to retrieve the unaligned data structure from the register and process the unaligned data structure ([0003], line 9, processing cores, [0023], lines 8-11, the result is provided along path 122 to the ROB 120 for storing into the ROB 120 or an allocated PRF and/or forwarding to another execution unit for use by another instruction or the like; [0020], lines 10-13, functional instructions, such as floating point instructions (e.g., media type instructions or the like) or integer instructions or the like, are dispatched to functional execution units (not shown)).
To any extent to which Di does not implicitly disclose the unaligned data structure has a length that is greater than a length of each of the at least two data chunks, Hammarlund explicitly discloses that an unaligned data structure has a length that is greater than a length of each of at least two data chunks ([0045], lines 7-10, referring to FIG. 5, addresses A and A+16 are the two unaligned accesses, while addresses X, Y and Z are the aligned 16B chunks of memory that are touched by the 256-bit access; in other words, the 256-bit data structure has a length that is greater than each of the three 128-bit chunks of memory). It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the teaching of Hammarlund with the invention of Di such that the unaligned data structure of Di has a length that is greater than a length of each of the at least two data chunks of Di, in order to support calculations on larger or more precise data. Alternatively, this modification merely entails combining prior art elements (Di’s teaching of an unaligned data structure and each of the at least two data chunks, in conjunction with Di’s teaching that alternative cache line sizes are contemplated and a data length is specified, and Hammarlund’s teaching that an unaligned data structure has a length that is greater than a length of each of at least two data chunks) according to known methods (Examiner submits that implementing data of larger length to support calculations on larger or more precise data) to yield predictable results (Di’s invention entailing an unaligned data structure and each of the at least two data chunks, wherein the unaligned data structure has a length that is greater than a length of each of the at least two data chunks), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
To any extent to which the combination of Di and Hammarlund does not implicitly entail that the register has a width that matches the length of the unaligned data structure but is different from lengths of each of the two data chunks, Roussel explicitly discloses a register to which an unaligned data structure is stored has a width that matches a length of the unaligned data structure ([0019], lines 12-13, there are eight XMM registers 84 and they are all 128-bits wide; [0026], lines 4-6, an instruction that includes an LDDQU instruction, which is an instruction that when executed causes a 128-bit unaligned operand to be obtained; [0029], lines 1-3, a LDDQU instruction specifies both a destination register (typically an XMM register) for storing the aligned operand).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Roussel with the combination of Di and Hammarlund in order to ensure correct program execution (relative to the register having less width, which may lead to lost data) and to save cost and space (relative to the register having more width, which is not wholly used to store the unaligned data structure). Alternatively, this modification merely entails combining prior art elements (the teaching of a register and unaligned data structure of the combination of Di and Hammarlund, and Roussel’s teaching of a register and unaligned data structure being the same width) according to known methods (Examiner submits that implementing data and a register which holds the data to be a same width is known) to yield predictable results (the combination of Di and Hammarlund entailing a register and unaligned data structure, wherein the register has a same width as the unaligned data structure), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143. Note that Roussel’s teaching of a register to which an unaligned data structure is stored having a width that matches a length of the unaligned data structure, when applied to the combination of Di and Hammarlund wherein the length of the unaligned data structure is different from lengths of each of the two data chunks, consequently results in the register having a width that is different from lengths of each of the two data chunks.
Consider claim 2, the overall combination entails the processor of claim 1 (see above), wherein start and end bits of the unaligned data structure do not align with start and end bits of the at least two data chunks (Di, [0024], lines 1-2, cache line unaligned load instruction; [0024], lines 7-12, the specified address points to a location within the current cache line and the data length otherwise extends beyond the current cache line to the next sequential cache line. Thus, the current cache line includes only a portion of the target data so that the cache line unaligned load instruction returns only a partial result; FIG. 2).
Consider claim 9, the overall combination entails the processor of claim 1 (see above), wherein the register has a same width as the unaligned data structure (Roussel, [0019], lines 12-13, there are eight XMM registers 84 and they are all 128-bits wide; [0026], lines 4-6, an instruction that includes an LDDQU instruction, which is an instruction that when executed causes a 128-bit unaligned operand to be obtained; [0029], lines 1-3, a LDDQU instruction specifies both a destination register (typically an XMM register) for storing the aligned operand).
Consider claim 10, Di discloses a core ([0003], line 9, processing cores), comprising: a load unit configured to retrieve data ([0020], lines 20-22, the term “MOB” is a common lexicon for a memory execution unit that executes memory type instructions, including load and store instructions; [0025], lines 1-3, the MOB 114 incorporates reload circuitry 124 that performs additional functions in the event that the load is a cache line unaligned load instruction; [0027], lines 23-24, it is noted that the reload circuitry 124, the memory 128 and the merge unit 130 may all be incorporated within the MOB 114 and may be considered as part of the MOB 114) from a memory that stores unaligned data structures ([0024], lines 1-5, if instead the load is a cache line unaligned load instruction, then the MOB 114 begins processing the load in a similar manner in which it uses the physical address, once determined, to access a portion of the data from a first cache line stored in the cache memory 116; [0023], lines 5-8, the MOB 114 uses the physical address to access the data from a cache line stored in the cache memory 116 (which may ultimately be retrieved from the system memory 118)); the load unit comprising circuitry ([0020], lines 20-22, the term “MOB” is a common lexicon for a memory execution unit that executes memory type instructions, including load and store instructions; [0025], lines 1-3, the MOB 114 incorporates reload circuitry 124 that performs additional functions in the event that the load is a cache line unaligned load instruction; [0027], lines 23-24, it is noted that the reload circuitry 124, the memory 128 and the merge unit 130 may all be incorporated within the MOB 114 and may be considered as part of the MOB 114) configured to: receive at least two data chunks from the memory using respective read cycles ([0024], lines 1-5, if instead the load is a cache line unaligned load instruction, then the MOB 114 begins processing the load in a similar manner in which it uses the physical address, once determined, to access a portion of the data from a first cache line stored in the cache memory 116; [0025], lines 28-33, the scheduler 112 is temporarily stalled for one cycle, and the same load instruction with the incremented address and the same data length is dispatched as the very next instruction just behind the original cache line unaligned load instruction), identify an unaligned data structure within the at least two data chunks ([0022], lines 1-4, the MOB 114 receives load instructions and determines whether the load is cache line aligned or unaligned. Each load instruction includes a specified address and a specified data length; [0024], lines 7-12, the specified address points to a location within the current cache line and the data length otherwise extends beyond the current cache line to the next sequential cache line. Thus, the current cache line includes only a portion of the target data so that the cache line unaligned load instruction returns only a partial result), wherein the unaligned data structure has a length that is greater than a length of each of the at least two data chunks ([0004], lines 15-16, alternative cache line sizes are contemplated; [0029], line 10, the specified data length is DL), and store the unaligned data structure in a register ([0021], lines 14-16, a load instruction, for example, retrieves data from the cache memory 116 and temporarily stores the data into the allocated register in the PRF; [0027], lines 20-23, the MOB 114 or the merge unit 130 then provides the merged result data via path 122 for storage in the ROB 120 or in the allocated register of the PRF (and forwarding, if applicable)), wherein the unaligned data structure spans across the at least two data chunks and does not align with the at least two data chunks ([0024], lines 1-2, cache line unaligned load instruction; [0024], lines 7-12, the specified address points to a location within the current cache line and the data length otherwise extends beyond the current cache line to the next sequential cache line. Thus, the current cache line includes only a portion of the target data so that the cache line unaligned load instruction returns only a partial result); and data processing circuitry configured to retrieve the unaligned data structure from the register and process the unaligned data structure ([0003], line 9, processing cores, [0023], lines 8-11, the result is provided along path 122 to the ROB 120 for storing into the ROB 120 or an allocated PRF and/or forwarding to another execution unit for use by another instruction or the like; [0020], lines 10-13, functional instructions, such as floating point instructions (e.g., media type instructions or the like) or integer instructions or the like, are dispatched to functional execution units (not shown)).
To any extent to which Di does not implicitly disclose the unaligned data structure has a length that is greater than a length of each of the at least two data chunks, Hammarlund explicitly discloses that an unaligned data structure has a length that is greater than a length of each of at least two data chunks ([0045], lines 7-10, referring to FIG. 5, addresses A and A+16 are the two unaligned accesses, while addresses X, Y and Z are the aligned 16B chunks of memory that are touched by the 256-bit access; in other words, the 256-bit data structure has a length that is greater than each of the three 128-bit chunks of memory). It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the teaching of Hammarlund with the invention of Di such that the unaligned data structure of Di has a length that is greater than a length of each of the at least two data chunks of Di, in order to support calculations on larger or more precise data. Alternatively, this modification merely entails combining prior art elements (Di’s teaching of an unaligned data structure and each of the at least two data chunks, in conjunction with Di’s teaching that alternative cache line sizes are contemplated and a data length is specified, and Hammarlund’s teaching that an unaligned data structure has a length that is greater than a length of each of at least two data chunks) according to known methods (Examiner submits that implementing data of larger length to support calculations on larger or more precise data) to yield predictable results (Di’s invention entailing an unaligned data structure and each of the at least two data chunks, wherein the unaligned data structure has a length that is greater than a length of each of the at least two data chunks), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
To any extent to which the combination of Di and Hammarlund does not implicitly entail that the register has a width that matches the length of the unaligned data structure but is different from lengths of each of the two data chunks, Roussel explicitly discloses a register to which an unaligned data structure is stored has a width that matches a length of the unaligned data structure ([0019], lines 12-13, there are eight XMM registers 84 and they are all 128-bits wide; [0026], lines 4-6, an instruction that includes an LDDQU instruction, which is an instruction that when executed causes a 128-bit unaligned operand to be obtained; [0029], lines 1-3, a LDDQU instruction specifies both a destination register (typically an XMM register) for storing the aligned operand).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Roussel with the combination of Di and Hammarlund in order to ensure correct program execution (relative to the register having less width, which may lead to lost data) and to save cost and space (relative to the register having more width, which is not wholly used to store the unaligned data structure). Alternatively, this modification merely entails combining prior art elements (the teaching of a register and unaligned data structure of the combination of Di and Hammarlund, and Roussel’s teaching of a register and unaligned data structure being the same width) according to known methods (Examiner submits that implementing data and a register which holds the data to be a same width is known) to yield predictable results (the combination of Di and Hammarlund entailing a register and unaligned data structure, wherein the register has a same width as the unaligned data structure), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143. Note that Roussel’s teaching of a register to which an unaligned data structure is stored having a width that matches a length of the unaligned data structure, when applied to the combination of Di and Hammarlund wherein the length of the unaligned data structure is different from lengths of each of the two data chunks, consequently results in the register having a width that is different from lengths of each of the two data chunks.
Consider claim 11, the overall combination entails the core of claim 10 (see above), wherein start and end bits of the unaligned data structure do not align with start and end bits of the at least two data chunks (Di, [0024], lines 1-2, cache line unaligned load instruction; [0024], lines 7-12, the specified address points to a location within the current cache line and the data length otherwise extends beyond the current cache line to the next sequential cache line. Thus, the current cache line includes only a portion of the target data so that the cache line unaligned load instruction returns only a partial result; FIG. 2).
Consider claim 18, the overall combination entails the core of claim 10 (see above), wherein the register has a same width as the unaligned data structure (Roussel, [0019], lines 12-13, there are eight XMM registers 84 and they are all 128-bits wide; [0026], lines 4-6, an instruction that includes an LDDQU instruction, which is an instruction that when executed causes a 128-bit unaligned operand to be obtained; [0029], lines 1-3, a LDDQU instruction specifies both a destination register (typically an XMM register) for storing the aligned operand).
Consider claim 19, Di discloses a method comprising: receiving, at a load unit ([0020], lines 20-22, the term “MOB” is a common lexicon for a memory execution unit that executes memory type instructions, including load and store instructions; [0025], lines 1-3, the MOB 114 incorporates reload circuitry 124 that performs additional functions in the event that the load is a cache line unaligned load instruction; [0027], lines 23-24, it is noted that the reload circuitry 124, the memory 128 and the merge unit 130 may all be incorporated within the MOB 114 and may be considered as part of the MOB 114), at least two data chunks from a memory using respective read cycles ([0024], lines 1-5, if instead the load is a cache line unaligned load instruction, then the MOB 114 begins processing the load in a similar manner in which it uses the physical address, once determined, to access a portion of the data from a first cache line stored in the cache memory 116; [0025], lines 28-33, the scheduler 112 is temporarily stalled for one cycle, and the same load instruction with the incremented address and the same data length is dispatched as the very next instruction just behind the original cache line unaligned load instruction), wherein the memory stores unaligned data structures ([0024], lines 1-5, if instead the load is a cache line unaligned load instruction, then the MOB 114 begins processing the load in a similar manner in which it uses the physical address, once determined, to access a portion of the data from a first cache line stored in the cache memory 116; [0023], lines 5-8, the MOB 114 uses the physical address to access the data from a cache line stored in the cache memory 116 (which may ultimately be retrieved from the system memory 118)); identifying an unaligned data structure within the at least two data chunks ([0022], lines 1-4, the MOB 114 receives load instructions and determines whether the load is cache line aligned or unaligned. Each load instruction includes a specified address and a specified data length; [0024], lines 7-12, the specified address points to a location within the current cache line and the data length otherwise extends beyond the current cache line to the next sequential cache line. Thus, the current cache line includes only a portion of the target data so that the cache line unaligned load instruction returns only a partial result), wherein the unaligned data structure has a length that is greater than a length of each of the at least two data chunks ([0004], lines 15-16, alternative cache line sizes are contemplated; [0029], line 10, the specified data length is DL); storing the unaligned data structure in a register ([0021], lines 14-16, a load instruction, for example, retrieves data from the cache memory 116 and temporarily stores the data into the allocated register in the PRF; [0027], lines 20-23, the MOB 114 or the merge unit 130 then provides the merged result data via path 122 for storage in the ROB 120 or in the allocated register of the PRF (and forwarding, if applicable)), wherein the unaligned data structure spans across the at least two data chunks and does not align with the at least two data chunks ([0024], lines 1-2, cache line unaligned load instruction; [0024], lines 7-12, the specified address points to a location within the current cache line and the data length otherwise extends beyond the current cache line to the next sequential cache line. Thus, the current cache line includes only a portion of the target data so that the cache line unaligned load instruction returns only a partial result); and retrieving the unaligned data structure from the register and processing the unaligned data structure using circuitry in a core ([0003], line 9, processing cores, [0023], lines 8-11, the result is provided along path 122 to the ROB 120 for storing into the ROB 120 or an allocated PRF and/or forwarding to another execution unit for use by another instruction or the like; [0020], lines 10-13, functional instructions, such as floating point instructions (e.g., media type instructions or the like) or integer instructions or the like, are dispatched to functional execution units (not shown)).
To any extent to which Di does not implicitly disclose the unaligned data structure has a length that is greater than a length of each of the at least two data chunks, Hammarlund explicitly discloses that an unaligned data structure has a length that is greater than a length of each of at least two data chunks ([0045], lines 7-10, referring to FIG. 5, addresses A and A+16 are the two unaligned accesses, while addresses X, Y and Z are the aligned 16B chunks of memory that are touched by the 256-bit access; in other words, the 256-bit data structure has a length that is greater than each of the three 128-bit chunks of memory). It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to combine the teaching of Hammarlund with the invention of Di such that the unaligned data structure of Di has a length that is greater than a length of each of the at least two data chunks of Di, in order to support calculations on larger or more precise data. Alternatively, this modification merely entails combining prior art elements (Di’s teaching of an unaligned data structure and each of the at least two data chunks, in conjunction with Di’s teaching that alternative cache line sizes are contemplated and a data length is specified, and Hammarlund’s teaching that an unaligned data structure has a length that is greater than a length of each of at least two data chunks) according to known methods (Examiner submits that implementing data of larger length to support calculations on larger or more precise data) to yield predictable results (Di’s invention entailing an unaligned data structure and each of the at least two data chunks, wherein the unaligned data structure has a length that is greater than a length of each of the at least two data chunks), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
To any extent to which the combination of Di and Hammarlund does not implicitly entail that the register has a width that matches the length of the unaligned data structure but is different from lengths of each of the two data chunks, Roussel explicitly discloses a register to which an unaligned data structure is stored has a width that matches a length of the unaligned data structure ([0019], lines 12-13, there are eight XMM registers 84 and they are all 128-bits wide; [0026], lines 4-6, an instruction that includes an LDDQU instruction, which is an instruction that when executed causes a 128-bit unaligned operand to be obtained; [0029], lines 1-3, a LDDQU instruction specifies both a destination register (typically an XMM register) for storing the aligned operand).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Roussel with the combination of Di and Hammarlund in order to ensure correct program execution (relative to the register having less width, which may lead to lost data) and to save cost and space (relative to the register having more width, which is not wholly used to store the unaligned data structure). Alternatively, this modification merely entails combining prior art elements (the teaching of a register and unaligned data structure of the combination of Di and Hammarlund, and Roussel’s teaching of a register and unaligned data structure being the same width) according to known methods (Examiner submits that implementing data and a register which holds the data to be a same width is known) to yield predictable results (the combination of Di and Hammarlund entailing a register and unaligned data structure, wherein the register has a same width as the unaligned data structure), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143. Note that Roussel’s teaching of a register to which an unaligned data structure is stored having a width that matches a length of the unaligned data structure, when applied to the combination of Di and Hammarlund wherein the length of the unaligned data structure is different from lengths of each of the two data chunks, consequently results in the register having a width that is different from lengths of each of the two data chunks.
Consider claim 20, the overall combination entails the method of claim 19 (see above), wherein start and end bits of the unaligned data structure do not align with start and end bits of the at least two data chunks (Di, [0024], lines 1-2, cache line unaligned load instruction; [0024], lines 7-12, the specified address points to a location within the current cache line and the data length otherwise extends beyond the current cache line to the next sequential cache line. Thus, the current cache line includes only a portion of the target data so that the cache line unaligned load instruction returns only a partial result; FIG. 2).
Claim(s) 4, 6, 13, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di, Hammarlund, and Roussel as applied to claims 1 and 10 above, and further in view of Quesada et al. (Quesada) (US 20230059970 A1).
Consider claim 4, the combination thus far entails the processor of claim 1 (see above), but does not entail that the unaligned data structures each comprise a plurality of mantissas and a shared exponent, wherein a length of each of the unaligned data structures is not a power of two.
On the other hand, Quesada discloses data structures each comprise a plurality of mantissas and a shared exponent, wherein a length of each of the data structures is not a power of two ([0058], lines 4-5, a 16-bit block floating point 815, a 12-bit block floating point 820; [0059], lines 1-8, the block floating point data type is a relatively new data type where the exponent is shared by multiple mantissas. For example, the 16-bit block floating point 815 includes an 8-bit exponent which is shared by 16, 7-bit mantissas. That is, there are 16 floating point values included within the single 16-bit block floating point value. The combination of the shared exponent and the 16 individual mantissas generate the 16 different floating point values; [0060], lines 1-5, the 12-bit block floating point 820 data type is similar in that it has an 8-bit exponent that is shared by 16 mantissas to represent 16 different floating point values. However, the mantissas for the 12-bit block floating point 820 data type are each only 3 bits).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Quesada with the combination of Di, Hammarlund, and Roussel in order to save space via the use of a shared exponent. Alternatively, this modification merely entails combining prior art elements (the unaligned data structures of the combination of Di, Hammarlund, and Roussel, and Quesada’s teaching of a particular data structure as cited above) according to known methods (Examiner submits that use of different data structures is known, as reflected by Quesada) to yield predictable results (the combination of Di, Hammarlund, and Roussel entailing unaligned data structures, wherein the unaligned data structures in particular each comprise a plurality of mantissas and a shared exponent, wherein a length of each of the unaligned data structures is not a power of two), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 6, the overall combination entails the processor of claim 4 (see above), wherein the unaligned data structures are one of a block floating points (BFP) or microscaling floating points (MXFP) (Quesada, [0058], lines 4-5, a 16-bit block floating point 815, a 12-bit block floating point 820; [0059], lines 1-8, the block floating point data type is a relatively new data type where the exponent is shared by multiple mantissas. For example, the 16-bit block floating point 815 includes an 8-bit exponent which is shared by 16, 7-bit mantissas. That is, there are 16 floating point values included within the single 16-bit block floating point value. The combination of the shared exponent and the 16 individual mantissas generate the 16 different floating point values; [0060], lines 1-5, the 12-bit block floating point 820 data type is similar in that it has an 8-bit exponent that is shared by 16 mantissas to represent 16 different floating point values. However, the mantissas for the 12-bit block floating point 820 data type are each only 3 bits).
Consider claim 13, the combination thus far entails the core of claim 10 (see above), but does not entail that the unaligned data structures each comprise a plurality of mantissas and a shared exponent, wherein a length of each of the unaligned data structures is not a power of two.
On the other hand, Quesada discloses data structures each comprise a plurality of mantissas and a shared exponent, wherein a length of each of the data structures is not a power of two ([0058], lines 4-5, a 16-bit block floating point 815, a 12-bit block floating point 820; [0059], lines 1-8, the block floating point data type is a relatively new data type where the exponent is shared by multiple mantissas. For example, the 16-bit block floating point 815 includes an 8-bit exponent which is shared by 16, 7-bit mantissas. That is, there are 16 floating point values included within the single 16-bit block floating point value. The combination of the shared exponent and the 16 individual mantissas generate the 16 different floating point values; [0060], lines 1-5, the 12-bit block floating point 820 data type is similar in that it has an 8-bit exponent that is shared by 16 mantissas to represent 16 different floating point values. However, the mantissas for the 12-bit block floating point 820 data type are each only 3 bits).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Quesada with the combination of Di, Hammarlund, and Roussel in order to save space via the use of a shared exponent. Alternatively, this modification merely entails combining prior art elements (the unaligned data structures of the combination of Di, Hammarlund, and Roussel, and Quesada’s teaching of a particular data structure as cited above) according to known methods (Examiner submits that use of different data structures is known, as reflected by Quesada) to yield predictable results (the combination of Di, Hammarlund, and Roussel entailing unaligned data structures, wherein the unaligned data structures in particular each comprise a plurality of mantissas and a shared exponent, wherein a length of each of the unaligned data structures is not a power of two), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 15, the overall combination entails the core of claim 13 (see above), wherein the unaligned data structures are one of a block floating points (BFP) or microscaling floating points (MXFP) (Quesada, [0058], lines 4-5, a 16-bit block floating point 815, a 12-bit block floating point 820; [0059], lines 1-8, the block floating point data type is a relatively new data type where the exponent is shared by multiple mantissas. For example, the 16-bit block floating point 815 includes an 8-bit exponent which is shared by 16, 7-bit mantissas. That is, there are 16 floating point values included within the single 16-bit block floating point value. The combination of the shared exponent and the 16 individual mantissas generate the 16 different floating point values; [0060], lines 1-5, the 12-bit block floating point 820 data type is similar in that it has an 8-bit exponent that is shared by 16 mantissas to represent 16 different floating point values. However, the mantissas for the 12-bit block floating point 820 data type are each only 3 bits).
Claim(s) 5 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di, Hammarlund, Roussel, and Quesada as applied to claims 4 and 13 above, and further in view of Ray et al. (Ray) (US 20210035258 A1).
Consider claim 5, the combination thus far entails the processor of claim 4 (see above), but does not explicitly entail the unaligned data structures each comprise metadata.
On the other hand, Ray discloses a data structure comprises metadata ([0433], lines 7-11, the first matrix is a sparse matrix, where elements of the first matrix are encoded into a sparse encoding, and where the sparse encoding includes a set of non-zero value elements and metadata to identify a location for the non-zero value elements).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ray with the combination of Di, Hammarlund, Roussel, and Quesada in order to facilitate processing of the unaligned data structures, in general, and/or to reduce memory use of the unaligned data structures in particular. Alternatively, this modification merely entails combining prior art elements (the unaligned data structures of the combination of Di, Hammarlund, Roussel, and Quesada, and Ray’s teaching of a data structure comprising metadata in general, and/or sparsity metadata in particular) according to known methods (Examiner submits that use of metadata and sparsity information is known, as reflected by the teaching of Ray) to yield predictable results (the combination of Di, Hammarlund, Roussel, and Quesada, entailing unaligned data structures, wherein the unaligned data structures each comprise metadata), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 14, the combination thus far entails the core of claim 13 (see above), but does not explicitly entail the unaligned data structures each comprise metadata.
On the other hand, Ray discloses a data structure comprises metadata ([0433], lines 7-11, the first matrix is a sparse matrix, where elements of the first matrix are encoded into a sparse encoding, and where the sparse encoding includes a set of non-zero value elements and metadata to identify a location for the non-zero value elements).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ray with the combination of Di, Hammarlund, Roussel, and Quesada in order to facilitate processing of the unaligned data structures, in general, and/or to reduce memory use of the unaligned data structures in particular. Alternatively, this modification merely entails combining prior art elements (the unaligned data structures of the combination of Di, Hammarlund, Roussel, and Quesada, and Ray’s teaching of a data structure comprising metadata in general, and/or sparsity metadata in particular) according to known methods (Examiner submits that use of metadata and sparsity information is known, as reflected by the teaching of Ray) to yield predictable results (the combination of Di, Hammarlund, Roussel, and Quesada entailing unaligned data structures, wherein the unaligned data structures each comprise metadata), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di, Hammarlund, Roussel, and Quesada as applied to claims 4 and 13 above, and further in view of Lo et al. (Lo) (US 20190347553).
Consider claim 7, the combination thus far entails the processor of claim 4 (see above). In addition, to any extent to which the combination thus far does not entail the data processing circuitry being configured to convert the unaligned data structure into a plurality of floating points using the plurality of mantissas and the shared exponent (via Quesada, paragraph [0059], lines 6-8, for example, which discloses that the combination of the shared exponent and the 16 individual mantissas generate the 16 different floating point values), Lo discloses data processing circuitry being configured to convert a data structure into a plurality of floating points using a plurality of mantissas and a shared exponent ([0017], lines 1-16, a mixed or hybrid precision computation process in some examples performs calculations in different format precisions to allow increased processing speeds at phases or stages that can be performed using lower precisions, while performing calculations at higher precisions at phases or stages that have a greater impact on the training process. For example, a mixed precision system in some examples uses both block floating point and single-precision floating point formats at different stages of the neural network training process. Switching between lower precision and higher precision formats (e.g., by converting between block floating point and 32-bit floating point formats, or other non-block floating point formats) allows for an optimized process that balances computational accuracy and speed of processing. As a result, a more efficient training of the neural network can be performed), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lo with the combination of Di, Hammarlund, Roussel, and Quesada in order to facilitate processing of the compressed data and to increase efficiency and balance computational accuracy and speed of processing. Alternatively, this modification merely entails combining prior art elements (the unaligned data structure entailing the plurality of mantissas and the shared exponent of the combination of Di, Hammarlund, Roussel, and Quesada, and the explicit teaching of Lo of converting that compressed data) according to known methods (Examiner submits that converting data from one format to another is well-known) to yield predictable results (the combination of Di, Hammarlund, Roussel, and Quesada, further entailing wherein the data processing circuitry is configured to convert the unaligned data structure into a plurality of floating points using the plurality of mantissas and the shared exponent), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 16, the combination thus far entails the core of claim 13 (see above). In addition, to any extent to which the combination thus far does not entail the data processing circuitry being configured to convert the unaligned data structure into a plurality of floating points using the plurality of mantissas and the shared exponent (via Quesada, paragraph [0059], lines 6-8, for example, which discloses that the combination of the shared exponent and the 16 individual mantissas generate the 16 different floating point values), Lo discloses data processing circuitry being configured to convert a data structure into a plurality of floating points using a plurality of mantissas and a shared exponent ([0017], lines 1-16, a mixed or hybrid precision computation process in some examples performs calculations in different format precisions to allow increased processing speeds at phases or stages that can be performed using lower precisions, while performing calculations at higher precisions at phases or stages that have a greater impact on the training process. For example, a mixed precision system in some examples uses both block floating point and single-precision floating point formats at different stages of the neural network training process. Switching between lower precision and higher precision formats (e.g., by converting between block floating point and 32-bit floating point formats, or other non-block floating point formats) allows for an optimized process that balances computational accuracy and speed of processing. As a result, a more efficient training of the neural network can be performed), and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lo with the combination of Di, Hammarlund, Roussel, and Quesada in order to facilitate processing of the compressed data and to increase efficiency and balance computational accuracy and speed of processing. Alternatively, this modification merely entails combining prior art elements (the unaligned data structure entailing the plurality of mantissas and the shared exponent of the combination of Di, Hammarlund, Roussel, and Quesada, and the explicit teaching of Lo of converting that compressed data) according to known methods (Examiner submits that converting data from one format to another is well-known) to yield predictable results (the combination of Di, Hammarlund, Roussel, and Quesada, further entailing wherein the data processing circuitry is configured to convert the unaligned data structure into a plurality of floating points using the plurality of mantissas and the shared exponent), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Claim(s) 8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di, Hammarlund, and Roussel as applied to claims 1 and 10 above, and further in view of Robinson et al. (Robinson) (US 20190138308 A1).
Consider claim 8, the combination thus far entails the processor of claim 1 (see above), but does not explicitly disclose that the processor further comprises: a store unit configured to store the unaligned data structure, after being processed by the data processing circuitry, into the memory using at least two data chunks and at least two write cycles.
On the other hand, Robinson discloses a processor further comprises: a store unit configured to store an unaligned data structure, after being processed by a data processing circuitry, into a memory using at least two data chunks and at least two write cycles ([0030], lines 1-4, the processor may execute the unaligned data store instruction to store in memory n consecutive unaligned data elements by performing only n+1 data write operations to memory; [0055], lines 1-2, The unaligned data structure to be loaded from/stored to memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Robinson with the combination of Di, Hammarlund, and Roussel in order to support the capability of storing unaligned data. Alternatively, this modification merely entails combining prior art elements (the teachings of Di, Hammarlund, and Roussel of an unaligned load instruction, including an unaligned data structure after being processed by the data processing circuitry, memory, and performing the unaligned load instruction via using at least two data chunks and at least two read cycles, and Robinson’s teaching as cited of an unaligned data store instruction alongside an unaligned data load instruction) according to known methods (Examiner submits that implementation of unaligned data store instructions in general was known, as well as unaligned data store instruction that were implemented in a manner analogous to a corresponding unaligned data load instruction, as reflected by Robinson) to yield predictable results (the processor of Di, Hammarlund, and Roussel, further comprising: a store unit configured to store an unaligned data structure, after being processed by a data processing circuitry, into a memory using at least two data chunks and at least two write cycles), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 17, the combination thus far entails the core of claim 10 (see above), but does not explicitly entail that the core further comprises: a store unit configured to store the unaligned data structure, after being processed by the data processing circuitry, into the memory using at least two data chunks and at least two write cycles.
On the other hand, Robinson discloses a core further comprises: a store unit configured to store an unaligned data structure, after being processed by a data processing circuitry, into a memory using at least two data chunks and at least two write cycles ([0030], lines 1-4, the processor may execute the unaligned data store instruction to store in memory n consecutive unaligned data elements by performing only n+1 data write operations to memory; [0055], lines 1-2, The unaligned data structure to be loaded from/stored to memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Robinson with the combination of Di, Hammarlund, and Roussel in order to support the capability of storing unaligned data. Alternatively, this modification merely entails combining prior art elements (the teachings of Di, Hammarlund, and Roussel of an unaligned load instruction, including an unaligned data structure after being processed by the data processing circuitry, memory, and performing the unaligned load instruction via using at least two data chunks and at least two read cycles, and Robinson’s teaching as cited of an unaligned data store instruction alongside an unaligned data load instruction) according to known methods (Examiner submits that implementation of unaligned data store instructions in general was known, as well as unaligned data store instruction that were implemented in a manner analogous to a corresponding unaligned data load instruction, as reflected by Robinson) to yield predictable results (the core of Di, Hammarlund, and Roussel, further comprising: a store unit configured to store an unaligned data structure, after being processed by a data processing circuitry, into a memory using at least two data chunks and at least two write cycles), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Di, Hammarlund, and Roussel as applied to claim 1, and further in view of Morris (US 20030188137 A1).
Consider claim 21, the combination thus far entails the processor of claim 1 (see above), wherein the lengths of each of the two data chunks is a power of two (Di, [0028], lines 7-8, the cache line length of the cache memory 116 is 64 bytes (64B); [0029], lines 4-5, load 16 bytes from the first cache line CL1; Hammarlund, [0045], line 9, 16B chunks of memory), but does not entail that the length of the register is not a power of two.
On the other hand, Morris discloses a length of a register that is not a power of two ([0045], lines 3-4, register lengths can vary and need not be a power of two).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Morris with the combination of Di, Hammarlund, and Roussel in order to ensure correct program execution (relative to the register having a length that is a power of two but is not long enough to wholly store desired-length data that is not a power of two, which may lead to lost data) and to save cost and space (relative to the register having a length that is a power of two but is longer and not wholly used to store desired-length data that is not a power of two)
Response to Arguments
Applicant on page 7 argues: “The Office objects to the Title and paragraphs [0049] and [0085]. Applicant has amended the Title and paragraphs [0037, 0049, and 0085] to address these objections.”
In view of the aforementioned amendments, the previously presented objections to the body of the specification are overcome. However, the objection to the title remains applicable — see the specification section above.
Applicant across pages 8-9 argues that the combination of references does not teach or suggest the newly amended claims.
While Examiner does not necessarily agree that the combination of references would not implicitly teach the newly amended claims, Examiner is newly relying upon Roussel reference for the purposes of compact prosecution — see the Claim Rejections - 35 USC § 103 section above.
Conclusion
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
Prosecution Insights