DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1 – 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu (U.S. Patent Publication No. 2022/0130776).
Regarding claim 1, in Figure 3B, Lu discloses an electronic device, comprising: an electronic component (30a) having a first group of terminals (comprising 10p, 10s) disposed on a lower surface of the electronic component and a second group of terminals (11c; conductive pads 11c, paragraph [0024]) disposed on an upper surface of the electronic component, wherein the first group of terminals comprise a first terminal (10p) and a second terminal (10s) disposed at different elevations; and a first group of conductive vias (11v; vias 11v disposed under component 30a) electrically connected to the first group of terminals (Figure 3B).
Regarding claim 2, Lu discloses a dielectric structure encapsulating the electronic component and the first group of conductive vias (Figure 3B).
Regarding claim 3, Lu discloses wherein the dielectric structure comprises a bottom encapsulant and a top encapsulant stacked over the bottom encapsulant, and the electronic component is embedded within the bottom encapsulant and the top encapsulant (Figure 3B).
Regarding claim 4, Lu discloses wherein the bottom encapsulant comprises a protruding portion in contact with the lower surface or a lateral surface extending between the upper surface and the lower surface of the electronic component (Figure 3B).
Regarding claim 5, Lu discloses wherein the upper surface of the electronic component has a central region closer to the bottom encapsulant and a peripheral region far away from the bottom encapsulant (Figure 3B).
Regarding claim 6, Lu discloses wherein the electronic component comprises a logic die and a carrier disposed between the first group of terminals and the logic die, and the logic die is configured to receive a power through the carrier (Figure 3B).
Regarding claim 7, Lu discloses wherein the first group of terminals comprise a first terminal at a central region of the lower surface and a second terminal at a peripheral region of the lower surface, and the first group of conductive vias has a first via connected to the first terminal and a second via connected to the second terminal, and a length of the first via is less than a length of the second via (Figure 3B).
Regarding claim 8, Lu discloses a second group of conductive vias connected to the second group of terminals, comprising a first via over a central region of the upper surface and a second via over a peripheral region of the upper surface, and a length of the first via is greater than a length of the second via (Figure 3B).
Regarding claim 9, Lu discloses wherein an arrangement of the first group of conductive vias and an arrangement of the second group of conductive vias are non-symmetrical with respect to the electronic component (Figure 3B).
2. Claims 10 – 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (U.S. Patent Publication No. 2023/0043512).
Regarding claim 10, in Figure 4 (with Figure 4 upside down), Lin discloses an electronic device, comprising: an electronic component (200A) having a lower surface and an upper surface; and a first group of conductive vias (comprising 154, 152) disposed under the lower surface of the electronic component and electrically connected to the electronic component (Figure 4), wherein the first group of conductive vias have different lengths (via 152 has a shorter length than via 154).
Regarding claim 11, Lin discloses a first circuit structure supporting the first group of conductive vias, wherein the first group of conductive vias comprise a first via and a second via, a top of the first via is at a first elevation with respect to an upper surface of the first circuit structure, and a top of the second via is at a second elevation, with respect to the upper surface of the first circuit structure, higher than the first elevation (Figure 4).
Regarding claim 12, Lin discloses wherein a bottom of the first via is at a third elevation, and a bottom of the second via is at a fourth elevation substantially the same as the third elevation with respect to the upper surface of the first circuit structure (Figure 4).
Regarding claim 13, Lin discloses a second group of conductive vias disposed over the upper surface of the electronic component and electrically connected to the electronic component, wherein the second group of conductive vias have different lengths (Figure 4).
Regarding claim 14, Lin discloses wherein a sum of a length of one of the first group of conductive vias and a length of one of the second group of conductive vias vertically overlapping the one of the first group of conductive vias is substantially identical to a sum of a length of another one of the first group of conductive vias and a length of another one of the second group of conductive vias directly over the another one of the first group of conductive vias (Figure 4).
Regarding claim 15, Lin discloses a second circuit structure disposed over the second group of conductive vias and connected to the second group of conductive vias, wherein the second group of conductive vias comprise a first via and a second via, a bottom of the first via is at a first elevation with respect to a lower surface of the second circuit structure, and a bottom of the second via is at a second elevation, with respect to the lower surface of the second circuit structure, higher than the first elevation (Figure 4).
Regarding claim 16, Lin discloses wherein the second via is closer to a side, extending between the upper surface and the lower surface, of the electronic component than to the first via (Figure 4).
Regarding claim 17, Lin discloses wherein a top of the first via is at a third elevation, and a top of the second via is at a fourth elevation substantially the same as the third elevation with respect to the lower surface of the second circuit structure (Figure 4).
3. Claims 18 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Satake et al. (U.S. Patent Publication No. 2024/0136268).
Regarding claim 18, in Figure 4, Satake discloses an electronic device, comprising: a lower circuit structure (103; circuit board 103) having a substantially flat surface; an electronic component (components 21, Figure 3D) disposed over the substantially flat surface of the lower circuit structure, wherein the electronic component has a lower curved surface facing the substantially flat surface (Figure 4); and first interconnections (105) disposed between the substantially flat surface of the lower circuit structure and the lower curved surface of the electronic component.
Regarding claim 19, Satake discloses wherein the electronic component has a first side and a second side opposite to the first side, and a bottom of the first side is at an elevation different from that of a bottom of the second side with respect to the substantially flat surface of the lower circuit structure (Figure 4).
Regarding claim 20, Satake discloses wherein the electronic component has a first side and a second side connected to the first side, and a bottom of the first side is at an elevation different from that of a bottom of the second side with respect to the substantially flat surface of the lower circuit structure (Figure 4).
Conclusion
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847