DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
2. This Application contains two distinct claim sets, both filed 06/03/2024, with no explicit indication as to which one is meant to be Examined in the instant application. Therefore, the Claim Set filed 06/03/2024 which is denoted by the Attorney Docket No. “TSMCP1299USB”, the same as that provided on the ‘Correspondence Information’ of the Instant Application, has been considered by the Examiner. Further, the Specification(s) denoted by Attorney Docket No. “TSMCP1299USB” has been considered by Examiner.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 06/03/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 10-13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (U.S. PG Pub No US2018/0308852A1).
Regarding claim 1, Lee teaches an integrated chip [see fig. 10B, 0001, 0010, 0032], comprising:
a semiconductor substrate (20) fig. 10B [0010-0011] comprising sidewalls that form a first fin (F1) [0042-0045] and a second fin (F2) [0042-0045] (see annotated fig. 10B below);
a dielectric material (22) fig. 10B [0012] arranged between (horizontally) the first fin (F1) and the second fin (F2);
a source/drain region (252) fig. 10B [0038, 0042] disposed on the first fin (F1) and the second fin (F2), wherein the source/drain region (252) continuously extends from directly over the first fin (F1) to directly over the second fin (F2); and
fin spacers (246) fig. 10B [0038] arranged over (above) the dielectric material (22) and covering lower sidewalls of the source/drain region (252), wherein the lower sidewalls comprise a first lower sidewall (LS1) (see annotated fig. 10B below) having a first height (H1) (defined as height above top of 22) and a second lower sidewall (LS2) that faces the first lower sidewall (LS1) and that has a second height (H2) (defined as height above top of 22), the first height (H1) different than (greater than) the second height (H2) (as defined in annotated fig. 10B below).
[AltContent: textbox (F2)][AltContent: textbox (F1)][AltContent: arrow][AltContent: textbox (LS3)][AltContent: arrow][AltContent: arrow][AltContent: textbox (LS1)][AltContent: textbox (LS2)][AltContent: textbox (H1)][AltContent: textbox (H2)][AltContent: textbox (H3)][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: arrow]
PNG
media_image2.png
25
14
media_image2.png
Greyscale
PNG
media_image2.png
25
14
media_image2.png
Greyscale
Annotated fig. 10B of Lee with close-up designating heights (H1-H3)
Regarding claim 2, Lee teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 1. Lee also teaches wherein the first lower sidewall (LS1) is in closer (nearest) proximity to the (right sidewall of) first fin (F1) than the second lower sidewall (LS2) (see annotated fig. 10B above).
Regarding claim 3, Lee teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 1. Lee also teaches wherein the lower sidewalls of the source/drain region (252) fig. 10B [0038, 0042] further comprise a third lower sidewall (LS3) (see annotated fig. 10B above) facing (outward) away from the first lower sidewall (LS1) and the second lower sidewall (LS2) (see annotated fig. 10B above), the third lower sidewall (LS3) having a third height (H3) (defined above top of 22) that is different than the first height (H1) and the second height (H2) (H2) (see annotated fig. 10B above).
Regarding claim 4, Lee teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 3. Lee also teaches wherein the third height (H3) is larger than either of the first height (H1) and the second height (H2).
Regarding claim 5, Lee teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 1. Lee also teaches wherein the source/drain region (252) fig. 10B [0038, 0042] continuously extends over (above) the first lower sidewall (LS1) and the second lower sidewall (LS2) (see annotated fig. 10B above).
Regarding claim 10, Lee teaches an integrated chip [see fig. 10B, 0001, 0010, 0032], comprising:
a semiconductor substrate (20) fig. 10B [0010-0011] comprising sidewalls that form a plurality of fins (F1-F2) [0042-0045] (see annotated fig. 10B below);
a dielectric material (22) fig. 10B [0012] arranged between (horizontally) the sidewalls (of Fins F1-F2);
epitaxial source/drain regions (152, 252) fig. 10B [0027, 0038, 0042] disposed over (above) the plurality of fins (F1-F2), wherein the epitaxial source/drain regions (comprising 252) comprise a first sidewall (S1) having a first height along a first (left) side of a first fin (F1) of the plurality of fins (F1-F2) and a second sidewall (S2) having a second height (H2) along a second (right) side of a second fin (F2) that faces the first (left) side of the first fin (F1), the first height (H1) different than the second height (H2) (H1, defined as uppermost height of 252 along fin F1 from top of 22 level – is greater than H2 defined as lowermost height of 252 along F2 sidewall from top of 22 level (as defined in annotated fig. 10B of Lee below); and
wherein the epitaxial source/drain regions (152, 252) fig. 10B [0027, 0038, 0042] are respectively asymmetric about a vertical line (VL1-2) (see annotated fig. 10B below) bisecting a bottommost surface of an associated one of the epitaxial source/drain regions (152/252) (asymmetric about off-center VL’s bisecting bottommost surfaces of 152/252 – as defined in annotated fig. 10B below).
[AltContent: oval][AltContent: textbox (Lower, right sidewall of 252 wrapping around uppermost surface of 252 (see claim 12)[img-media_image3.png])][AltContent: connector][AltContent: arrow][AltContent: textbox (VL2)][AltContent: textbox (VL1)][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: textbox (H2[img-media_image3.png])][AltContent: textbox (H1)][AltContent: connector][AltContent: textbox (F2)][AltContent: textbox (F1)][AltContent: arrow][AltContent: textbox (LS3)][AltContent: arrow][AltContent: arrow][AltContent: textbox (LS1)][AltContent: textbox (LS2)]
PNG
media_image2.png
25
14
media_image2.png
Greyscale
PNG
media_image2.png
25
14
media_image2.png
Greyscale
Annotated fig. 10B of Lee with close-up designating heights (H1-H3)
Regarding claim 11, Lee teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 10. Lee also teaches further comprising:
a fin spacer (246) fig. 10B [0038] arranged over the dielectric material (22) fig. 10B [0012] and covering a lower sidewall (lower, inner sidewalls of 252 bordering 246) of the epitaxial source/drain regions.
Regarding claim 12, Lee teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 11. Lee also teaches wherein the epitaxial source/drain regions (152, 252) fig. 10B [0027, 0038, 0042] comprise a first source/drain region (252) that wraps around a topmost surface of the fin spacer (246) FIG. 10b [0038] to a lower surface of the first source/drain region (252) that is both vertically below the topmost surface of the fin spacer (246) and along an outer sidewall of the fin spacer (246) that faces away from the first source/drain region (252) (see annotated fig. 10B of Lee above).
Regarding claim 13, Lee teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 10. Lee also teaches wherein the epitaxial source/drain regions (152, 252) fig. 10B [0027, 0038, 0042] respectively have a curved upper surface (uppermost surface of each s/d 152, 252… curved) facing away (facing at least partially, diagonally away) from the semiconductor substrate (20) fig. 10B [0010-0011].
Regarding claim 15, Lee teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 10. Lee also teaches wherein the plurality of fins (F1-F2) respectively have tapered widths (tapered above level where source/drain regions 152/252 adjoin fins comprising F1-F2; see annotated fig. 10B of Lee above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub No US2018/0308852A1), as applied in claim 1 above, in view of Bauer (U.S. PG Pub No US2011/0117732A1).
Regarding claim 6, Lee teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 1. However, Lee does not explicitly disclose wherein the source/drain region (252) fig. 10B [0038, 0042] comprises a plurality of different layers stacked onto surfaces of one another (only one 252 layer shown).
Bauer teaches an integrated chip (100) fig. 2G [0043, 0060] wherein the source/drain region (114) fig. 2G [0059] comprises a plurality of different layers (comprising 125, 135, 145) fig. 2G [0047, 0056, 0059] stacked (vertically) onto (supported by) surfaces of one another.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated chip of Lee such that the source/drain regions comprise a plurality of stacked epitaxial layers having distinct material compositions [0047, 0056, 0059] in order to optimize bottom-up growth [0025, 0060] of the epitaxial source/drain regions to efficiently and stably fill the target space with material [0059-0060], as taught by Bauer.
Regarding claim 8, Lee in view of Bauer teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 6. Lee in view of Bauer (with reference to Bauer) also teaches wherein the plurality of different layers (comprising 125, 135, 145) fig. 2G [0047, 0056, 0059] comprise a first semiconductor material layer (125) [0047], a second semiconductor material layer (135) [0056] arranged (directly) on an upper (top) surface and sidewalls (slanted right/left sidewalls) of the first semiconductor material layer (125), and a third semiconductor material layer (145) [0059] arranged on an upper (top) surface of the second semiconductor material layer (135) (each epitaxial material silicon-based semiconductor [0026-0029]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub No US2018/0308852A1) modified by Bauer (U.S. PG Pub No US 2011/0117732 A1), as applied in claim 6 above, and further in view of Tsai (U.S. PG Pub No US2014/0264575A1).
Regarding claim 7, Lee in view of Bauer teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 6. Lee in view of Bauer (with reference to Bauer) also teaches wherein the plurality of different layers (comprising 125, 135, 145) fig. 2G [0047, 0056, 0059] include:
a silicon arsenic layer (125) [0047] (could have arsenic n-dopant [0048]);
a first silicon phosphorous layer (135) [0056] (could be phosphorous n-doped, different from 125 composition [0057, 0051, 0048]) disposed over the silicon arsenic layer (125) and having a first (non-zero) doping concentration of phosphorous [0050]; and
a second silicon phosphorous layer (145) [0059] disposed over the first silicon phosphorous layer (135) (cycle may be repeated [0059] to deposit an additional phosphorous doped [0050, 0051, 0057] material over 135).
However, Lee in view of Bauer does not explicitly disclose a/the second silicon phosphorous layer (145) having a second doping concentration of phosphorous that is less than the first doping concentration of phosphorous (of 135) (relative phosphorous concentrations not specified [0050, 0057, 0059]).
Tsai teaches an integrated chip (150) fig. 7 [0026, 0058] comprising a second silicon phosphorous layer (215B) fig. 7 [0058] having a second doping concentration [0060] of phosphorous that is less than [0059] the first doping concentration of phosphorous (of 215A) fig. 7 [0058] (215B may be formed with ‘lower dopant level’ of phosphorus in Si:P material [0059]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the epitaxial source/drain layers of Lee in view of Bauer such that the upper Si:P epitaxial layer is formed with a lesser concentration of phosphorous than the lower Si:P epitaxial layer [0058-0059] in order to dope the materials to optimal levels [0058-0062] for reduced external resistance [0055] and improved device performance efficiency [0055], as taught by Tsai.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub No US2018/0308852A1) modified by Bauer (U.S. PG Pub No US 2011/0117732 A1), as applied in claim 6 above, and further in view of Li (U.S. PG Pub No US2019/0280115A1).
Regarding claim 9, Lee in view of Bauer teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 6. However, Lee does not explicitly disclose wherein the first height (H1) is in a range of between approximately 2 nanometers (nm) and approximately 6 nm and the second height (H2) is in a range of between approximately 0.1 nm and approximately 2 nm (heights of fin spacers 246 not explicitly disclosed).
Li teaches an integrated circuit chip wherein the first height (of left 55) fig. 14 [0048-0049] is in a range of between approximately 2 nanometers (nm) and approximately 6 nm (may be 1-10nm [0048], encompassing claimed range) and the second height (of right 55) fig. 14 [0048-0049] is in a range of between approximately 0.1 nm and approximately 2 nm (may be 1-10nm [0048], overlapping claimed range) (see further discussion below).
With respect to Li disclosing “the first height … is in a range of approximately 2 nm and approximately 6 nm” and “the second height … is in a range of between approximately 0.1nm and approximately 2 nm” – [0048] of Li discloses that “the height .. of the fin spacers … is in a range from about 1 nm to about 10 nm in some embodiments”. This range at least partially overlaps with the recited ranges for both the first and second fin spacers, and both conditions could be addressed if the first and second fin spacers were formed with heights of, for example, approximately 2 nm, within the range of Li [0048 Li]. Therefore, in the absence of evidence of criticality for the narrower ranges recited in the claims, one of ordinary skill in the art would consider the claimed heights obvious over the overlapping range(s) suggested in [0048] of Li. (See MPEP 2144.05, I).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have formed the fin spacers of Lee along the fins to heights of approximately 1-10 nm [0048 Li] in order to provide an optimal degree of isolating spacer material over the sidewalls of the fins [0048-0050] according to art recognized suitable parameters [0048], as taught by Li.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub No US2018/0308852A1), as applied in claim 10 above, in view of Li (U.S. PG Pub No US2019/0229197A1).
Regarding claim 14, Lee teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 10. However, Lee does not explicitly disclose also teaches further comprising:
a doped material disposed over the epitaxial source/drain regions (152, 252) fig. 10B [0027, 0038, 0042], the doped material having strands extending outward from two lower surfaces of the doped material that contact neighboring ones of the epitaxial source/drain regions (152, 252) fig. 10B [0027, 0038, 0042] to directly between sidewalls of the neighboring ones of the epitaxial source/drain regions (152, 252), as viewed in a cross-sectional view.
Li teaches an integrated chip [see fig. 15, 0070-0072] further comprising:
a doped material (101) fig. 15 [0058] (doped with carbon and/or phosphorous [0058]) (see fig. 14 for label) disposed over the epitaxial source/drain regions (61, 62 of 63) fig. 15 [0056] (see fig. 14 for label), the doped material (101) having strands (2 diagonally oriented sidewalls) extending outward from two lower surfaces (bordering, lower sidewalls) of the doped material that contact neighboring ones of the epitaxial source/drain regions (where 61, 62 meet) fig. 10B [0027, 0038, 0042] to directly between (upper) sidewalls of the neighboring ones of the epitaxial source/drain regions (61, 62 of 63) as viewed in a cross-sectional view (see fig. 14, fig. 15 perspectives).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have provided an additional epitaxial capping layer [0056-0058] over the source/drain region(s) of Lee in order to avoid extra junction capacitance [0084] and reduce defect noise [0084] in the integrated device, as taught by Li.
Claims 16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub No US2018/0308852A1) in view of Cho (U.S. PG Pub No US2020/0027895A1).
Regarding claim 16, Lee teaches an integrated chip [see fig. 10B, 0001, 0010, 0032], comprising:
a semiconductor substrate (20) fig. 10B [0010-0011] comprising sidewalls that form a first fin (F1) and a second fin (F2) [0042-0045] (see annotated fig. 10A below);
an insulating material (22) fig. 10B [0012] arranged (horizontally) between the first fin (F1) and the second fin (F2);
a first source/drain segment (left 252) fig. 10A [0038, 0042] disposed (directly) on the first fin (F1);
a second source/drain segment (right 252) fig. 10A [0038, 0042] disposed (directly) on the second fin (F2);
fin spacers (246) fig. 10B [0038] arranged over the insulating material (22) and on opposing sides of the first source/drain segment (left 252), wherein the fin spacers (246) extend to different heights (H1 vs H2) along the opposing sides (LS1, LS2) of the first source/drain segment (252) (as defined in annotated fig. 10B of Lee below).
[AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (F1)][AltContent: textbox (F2)]
PNG
media_image4.png
931
1187
media_image4.png
Greyscale
[AltContent: arrow][AltContent: textbox (D2[img-media_image5.png])][AltContent: arrow][AltContent: textbox (D1[img-media_image5.png])][AltContent: connector][AltContent: connector][AltContent: arrow][AltContent: textbox (LR)][AltContent: arrow][AltContent: textbox (UBR)][AltContent: rect][AltContent: rect][AltContent: textbox (F1)][AltContent: arrow][AltContent: textbox (LS3)][AltContent: arrow][AltContent: arrow][AltContent: textbox (LS1)][AltContent: textbox (LS2)][AltContent: textbox (H1)][AltContent: textbox (H2)][AltContent: connector][AltContent: connector][AltContent: arrow]
PNG
media_image2.png
25
14
media_image2.png
Greyscale
PNG
media_image2.png
25
14
media_image2.png
Greyscale
Annotated fig. 10A and fig. 10B of Lee with close-up designating heights (H1-H3)
However, Lee does not explicitly disclose a doped material continuously extending from directly over the first source/drain segment (left 252), to directly between outermost sidewalls of the first source/drain segment (let 252) and the second source/drain segment (right 252) that face one another (see fig. 10A perspective), and to directly over the second source/drain segment (right 252).
Cho teaches an integrated chip (100f) fig. 10B [0069-0071] comprising a doped material (154) fig. 10B [0034] continuously extending from directly over the first source/drain segment (left 153) fig. 10B [0034, 0071], to directly between outermost sidewalls of the first source/drain segment (left 153) and the second source/drain segment (right 153) [0034, 0071] that face one another (see fig. 10B perspective), and to directly over the second source/drain segment (right 153).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the source/drain epitaxial segments of Lee to include an additional doped epitaxial layer [0069-0071, 0034] connecting the source/drain segments above individual fins [0069-0071] in order to improve various electrical resistance [0053] and stress characteristics [0053] of the device, as taught by Cho.
Regarding claim 17, Lee in view of Cho teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 16. Lee also teaches wherein the first source/drain segment (left 252) fig. 10A [0038, 0042] vertically (directly) contacts an upper surface of the fin spacers (246) fig. 10B [0038].
Regarding claim 20, Lee in view of Cho teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 16. Lee also teaches wherein the first source/drain segment (left 252) fig. 10A [0038, 0042] comprises an upper bulbous region (UBR) (see close-up of annotated fig. 10B above) disposed over a lower region (LR) (see close-up of annotated fig. 10B above) confined between the fin spacers (246) fig. 10B [0038], the upper bulbous region (UBR) extending in a first (vertical) direction to a first distance (D1) past (vertically beyond) the lower region (LR) and further extending in a second (diagonal) direction to a second distance (D2) past (diagonally beyond) the lower region (L2), the first distance (D1) being different than (greater than) the second distance (D2) (as defined in annotated fig. 10B of Lee above).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub No US2018/0308852A1) modified by Cho (U.S. PG Pub No US2020/0027895A1), as applied in claim 16 above, and further in view of Yeo (U.S. PG Pub No US2019/0123161A1).
Regarding claim 18, Lee in view of Cho teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 16. However, Lee in view of Cho (with reference to Cho) does not explicitly disclose further comprising:
a silicide arranged over and directly between sidewalls of the doped material (153); and
an interconnect contact disposed on the silicide.
Yeo teaches an integrated chip [see fig. 9, 0096] further comprising:
a silicide (222) fig. 9 [0088-0089, 0064] arranged over and directly between sidewalls of the doped material (132) fig. 9 [0079]; and
an interconnect contact (210) fig. 9 [0090] disposed on (supported by) the silicide.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the doped epaxial source/drain region(s) of Lee in view of Cho to further comprise the silicide material [0088-0089, 0064] and contact plug of Yeo in order to physically and electrically connect the source/drain epitaxial region(s) [0088] to the contact plug [0090] to enhance electrical interconnectivity of the device [0088-0090, 0064], as taught by Yeo.
Regarding claim 19, Lee in view of Cho teaches the integrated chip [see fig. 10B, 0001, 0010, 0032] of claim 16. Lee in view of Cho (with reference to Cho) also teaches further comprising:
a second doped material (154) fig. 10B [0069-0071, 0034] arranged on the doped material (153) fig. 10B [0069-0071, 0034].
However, Lee in view of Cho does not explicitly disclose
a silicide arranged directly between sidewalls of the second doped material.
Yeo teaches an integrated chip [see fig. 9, 0096] comprising a silicide (222) fig. 9 [0088-0089, 0064] arranged directly between sidewalls of the second doped material (134) fig. 9 [0079].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the doped epaxial source/drain region(s) of Lee in view of Cho to further comprise the silicide material [0088-0089, 0064] and contact plug of Yeo in order to physically and electrically connect the source/drain epitaxial region(s) [0088] to the contact plug [0090] to enhance electrical interconnectivity of the device [0088-0090, 0064], as taught by Yeo.
Conclusion
14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature devices with doped epitaxial source/drain regions disposed over fins.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN AYERS WINTERS/Examiner, Art Unit 2892 08/02/2026
Prosecution Insights