DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5, 7, 9, 10, 12, 14, 15, 17 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shen et al. (U.S. PG Pub. # 2024/0219630 A1).
In Re claim 1, ‘630 teaches a co-packaged optical and electrical device, comprising: a package substrate (110); an electrical or opto-electrical chip (120a, par. 0031) disposed on the package substrate; a photonic integrated interconnect unit disposed on the package substrate, comprising: a photonic integrated circuit (PIC) (130) comprising a PIC waveguide (131); a plurality of interconnects (121a, 111a) connecting the electrical or opto-electrical chip to the photonic integrated interconnect unit, wherein the interconnects are formed on or in the package substrate; and a plurality of optical structures (111b) configured to connect the photonic integrated interconnect unit to a fiber optic cable, the plurality of optical structures comprising: a substrate waveguide (111b) formed on or in the package substrate, wherein the substrate waveguide is coupled to the PIC waveguide via evanescent coupling (par. 0025).
In Re claim 3, ‘630 teaches wherein the PIC comprises: a first layer (131); and a second layer (other 131 or electrical device as taught in par.0034, fig. 1).
In Re claim 5, ‘630 teaches wherein the package substrate is a glass substrate (par. 0036), comprising: a first layer comprising a glass material; and a second layer comprising a silicon oxide (SiO.sub.x), a copper, silicon nitride (SiN), or a combination thereof (pars. 0036 – 0039).
In Re claim 7, ‘630 teaches wherein the package substrate is a silicon substrate, comprising: a first layer comprising a Si material, an α-Si, a metal, or a combination thereof; and a second layer comprising a silicon oxide (SiO.sub.x), a copper, silicon nitride (SiN), or a combination thereof (pars. 0036 – 0039).
In Re claim 9, ‘630 teaches a co-packaged optical and electrical device, comprising: a package substrate (110); an integrated electrical or opto-electrical chip disposed on the package substrate, comprising: an electrical or opto-electrical chip (120a, par. 0031) disposed on the package substrate; and a photonic integrated interconnect unit disposed on the package substrate, comprising: a first photonic integrated circuit (PIC) comprising a first PIC waveguide (1 of the 3 of 111a, figs. 1 and 2); a second PIC comprising a second PIC waveguide (another of 111a or any other 111 of fig. 2 or one of 131); and a plurality of optical structures (111b, and 121b) configured to connect the photonic integrated interconnect unit to a fiber optic cable, the plurality of optical structures comprising: a substrate waveguide (121b) formed on or in the package substrate, wherein the substrate waveguide is coupled to the first PIC waveguide and the second PIC waveguide via evanescent coupling (pars. 0025, 0026).
In Re claim 10, ‘630 teaches wherein the package substrate is a glass substrate, comprising: a first layer comprising a glass material; and a second layer comprising a silicon oxide (SiO.sub.x), a copper, silicon nitride (SiN), or a combination thereof (pars. 0036 – 0039).
In Re claim 12, ‘630 teaches wherein the package substrate is a silicon substrate, comprising: a first layer comprising a Si material, an α-Si, a copper or a combination thereof; and a second layer comprising a silicon oxide (SiO.sub.x), a copper, silicon nitride (SiN), or a combination thereof (pars. 0036 – 0039).
In Re claim 14, ‘630 teaches a co-packaged optical and electrical device, comprising: a package substrate (110); a photonic integrated interconnect unit (140) disposed on the package substrate, comprising: a photonic integrated circuit (PIC) comprising a PIC waveguide (121), wherein the PIC waveguide is disposed in the PIC (fig. 4); an electrical or opto-electrical chip (150, pars. 0031, 0033, 0040) disposed on the photonic integrated interconnect unit; and a plurality of optical structures (111, 131) configured to connect the photonic integrated interconnect unit to a fiber cable (on another 120), the plurality of optical structures comprising: a substrate waveguide (111 or 131) formed on or in the package substrate, wherein the substrate waveguide is coupled to the PIC waveguide via evanescent coupling (par. 0025, 0026).
In Re claim 15, ‘630 teaches wherein the PIC comprises: a first layer (121 or 1213); and a second layer (1215).
In Re claim 17, ‘630 teaches wherein the package substrate is a glass substrate, comprising: a first layer comprising a glass material; and a second layer comprising a silicon oxide (SiO.sub.x), a copper, silicon nitride (SiN), or a combination thereof (pars. 0036 – 0039).
In Re claim 19, ‘630 teaches wherein the package substrate is a silicon substrate, comprising: a first layer comprising a Si material, an α-Si, a copper or a combination thereof; and a second layer comprising a silicon oxide (SiO.sub.x), a copper, silicon nitride (SiN), or a combination thereof (pars. 0036 – 0039).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 4, 6, 8, 11, 13, 16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (U.S. PG Pub. # 2024/0219630 A1).
In Re claim 2, ‘630 is silent to a PCB. However, it is well known in the art to attach an interposer (package substrate) such as 110 to a PCB so as to allow for electrical signals from external processing units to communicate with chips on interposers so as to direct optical communication as desired.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place the interposer (package substrate) 110 of ‘630 onto a PCB so as to allow for electrical signals from external processing units to communicate with the chips on the package substrate so as to direct optical communication as desired as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp.
In Re claims 4 and 16, ‘630 teaches the device of claims 3 and 15, respectively, and the first layer being waveguide 131 or 121 and that waveguides in the package substrate are silicon nitride (par. 0039) and that the PIC comprises electrical devices as taught in pars. 0033, 0034, but is silent to wherein: the first layer comprises a silicon oxide (SiO.sub.x), a copper, silicon nitride (SIN), or a combination thereof; and the second layer comprises a silicon (Si), an amorphous silicon (α-Si), a metal such as copper, or a combination thereof.
However, its well known in the art to use the same material for waveguides that couple to one another so as to ensure optimum optical coupling and to use metal such as copper to form electrical devices so as to ensure optimum electrical conductivity.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the first layer, waveguide 131, of silicon nitride so as to ensure optimum coupling with waveguides 111 and to use metal as the makeup of the electrical devices of 120 so as to ensure optimum electrical conductivity as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp.
In Re claims 6, 8, 11, 13, 18 and 20, ‘630 teaches the claimed layer but is expressly silent to the claimed thickness ranges. However, making the claimed layers to have about the claimed thicknesses is well known in the art so as to allow for optical and electrical signals to traverse while maintaining compact structural integrity of the layers. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the claimed layers to have about the claimed thicknesses so as to ensure not only a compact robust package but also allow for optimum electrical and optical signal traversal as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAD SMITH whose telephone number is (571)270-1294. The examiner can normally be reached M-F 7:30 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 1-571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHAD H SMITH/Primary Examiner, Art Unit 2874 Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAD SMITH whose telephone number is (571)270-1294. The examiner can normally be reached M-F 7:30 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 1-571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHAD H SMITH/Primary Examiner, Art Unit 2874
