DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election
Applicant’s election of claims #1-10 in the reply filed on June 19, 2026 is acknowledged. Because the Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claims #11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant is reminded that withdrawn method claim 11 must recite all the limitations of potentially allowable claim 1 in order to be eligible for rejoinder.
IDS
The IDS document(s) filed on June 4, 2024 has been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Specifications
The title is objected to because a more descriptive title is requested.
Claim Rejections – 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
As to claim 1, it is unclear if “a complementary metal oxide semiconductor (CMOS) layer” comprises CMOS device structures as the subsequent limitation “and including a plurality of display driving circuits” does not recite any CMOS device structures. The Examiner instead assumes “a CMOS layer” is merely an intended use label.
No Prior Art Applied
No prior art has been applied to the claims because the Examiner was unable to find the limitation “a transistor layer…and including a plurality of pixel driving circuits connected to the plurality of display driving circuits through a contact hole in the semiconductor wafer substrate…and including a light emitting element driven by the plurality of pixel driving circuits” as recited in claim 1.
As to claim 1, Kang et al. (U.S. Patent Publication No. 2022/0285452 A1), hereafter “Kang”, is the closest prior art. Kang teaches in FIG. 2A a display panel 1, wherein the display panel includes: a substrate 100 (not explicitly disclosed as a semiconductor wafer but obvious to one of ordinary skill in the art to select a semiconductor wafer material); a complementary metal oxide semiconductor (CMOS) layer IL (using the above 35 U.S.C. § 112(b) rejection interpretation) disposed on a first (top) side of the substrate and including a plurality of display driving circuits PCm, PCa that are driven independently of each other (paragraph [0092]); a transistor layer IL’ disposed on a second (bottom) side of the substrate; a light emitting element layer DISL disposed on (in proximity, not directly on) the second (bottom) side of the substrate and including a light emitting element EDm, EDa; an encapsulation layer PB disposed on the second (bottom) side of the substrate.
The Examiner brings attention to the limitation “a plurality of display driving circuits that are driven independently of each other” which differs from typical language requiring the display driving circuits themselves performing the independent driving of relevant pixel structure.
However, Kang does not teach the transistor layer…including a plurality of pixel driving circuits connected to the plurality of display driving circuits through a contact hole in the semiconductor wafer substrate…and including a light emitting element driven by the plurality of pixel driving circuits and no other prior art was found.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm.
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/SUBERR L CHI/Primary Examiner, Art Unit 2893
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