Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The applicant’s most recent amendment, filed on 8/21/2026, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered; the pending claims are 1-20.
Election/Restrictions
Election was made without traverse in the reply filed on 8/21/2026. Applicant has elected Group II, corresponding to claims 1-14. Invention Group I, corresponding to claims 15-20, is withdrawn from further consideration.
Drawings
The drawings submitted on 6/05/2024 have been accepted by the examiner.
Information Disclosure Statements
The information disclosure statements (IDS) submitted thus far have been considered by the examiner.
Specification
The specification is objected to under 37 CFR 1.71 as containing the following informalities. Appropriate correction is required.
Paragraph [0044] identifies the channels flanking electrical isolation 312 as channel 306b of first cell 301 and channel 306a of second cell 303. FIG. 3 labels 306a at the outer edge of cell 301 and 306b at the outer edge of cell 303, and the two channels that in fact flank isolation 312 carry no reference numeral. Either the text or the figure labeling is in error. The same paragraph refers to word line trench 320; the word line trench is 308, and 320 is the word line.
Paragraph [0052] states that gate dielectric 311 may be formed along channels 316a and 316b. The channels are 306a and 306b; 316 is the second dielectric layer.
Paragraph [0058] describes the second dielectric layer 316 but states that the first dielectric may include lanthanum species and silicon nitrite. It appears that second is intended.
Paragraphs [0061] and [0062] use region 315 and region 317 for the regions between the word line and the dielectric layers. Paragraph [0053] assigns 315 and 317 to the first and second sides of word line trench 308. One numeral is used for two different structures.
Claim Objections
Claims 3 and 13 are objected to because of the following informalities. Appropriate correction is required.
Claim 3 recites a first dielectric layer extending from a first end a word line trench. It appears that from a first end of a word line trench is intended.
Claim 13 recites wherein electrical isolation comprises. The antecedent recitation in claim 10 is an electrical isolation; it appears that wherein the electrical isolation comprises is intended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites that the second dielectric layer comprises an oxide containing one or more lanthanum species, silicon nitrite, or combinations thereof. A nitrite is a salt or ester of nitrous acid, and silicon nitrite has no recognized meaning as a dielectric material. The specification uses the same term at [0058] and nowhere defines it, so the scope of the claim cannot be determined with reasonable certainty. Paragraph [0045] of the specification recites silicon nitride. Replacing silicon nitrite with silicon nitride would overcome this rejection; because the specification repeats silicon nitrite, such an amendment would have to be supported as the correction of an evident error. For purposes of examination, silicon nitrite is interpreted as silicon nitride.
Claim 10 recites the second dynamic random access memory cell. The only earlier recitation is a second vertical dynamic random access memory cell; the term as recited lacks exact antecedent basis. In addition, the recitation that the first vertical dynamic random access memory cell and the second dynamic random access memory cell comprise a bit line arranged in a fi rst horizontal direction, a first channel, a second channel, and a word line arranged in a second horizontal direction between the first channel and the second channel, leaves it unclear whether the two cells together comprise one set of the recited elements or each cell comprises its own set. Claim 11, reciting that the cells each comprise only one word line for every two channels, and FIG. 3, which shows one word line 320 in each of cells 301 and 303, support the latter. For purposes of examination, claim 10 is interpreted as reciting the second vertical dynamic random access memory cell and as requiring each cell to comprise a first channel, a second channel and a word line between them, with a bit line arranged in the first horizontal direction that may be common to both cells. Inserting vertical and reciting each comprise would overcome this rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 10-13 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Yang-182 (US # 20210351182).
Regarding Claim 1, Yang-182 teaches a vertical dynamic random-access memory (DRAM) cell (transistor 110 in FIG. 1A, the access device of DRAM cell 402 in FIG. 4; [0030], [0089-91]), comprising:
a bit line (first conductive line 104 in FIG. 1A; [0032]) arranged in a first horizontal direction (X-direction FIG. 1A; [0031]);
a first channel (116a);
a second channel (116b); and
a shared word line (second conductive line 136, serving as gate electrode structure 108) arranged in a second horizontal direction (Y-direction) between the first channel and the second channel (108 between 116a and 116b in FIG. 1B);
wherein the first channel and the second channel extend in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction (shown in FIG. 1A, Z-direction against X and Y) such that the bit line intersects with a source/drain region of the first channel and the second channel (116a and 116b on lower conductive contact 105, which stands on line 104, in FIG. 1A; [0035, 37, 47]), and the shared word line intersects with a gate region of both the first channel and second channel (108 around 116a and 116b through gate dielectric material 112 in FIG. 1B; [0041, 44, 63]).
Regarding Claim 2, Yang-182 teaches the vertical dynamic random-access memory (DRAM) cell of claim 1, wherein the vertical dynamic random access memory (DRAM) cell contains only one word line for every two channels (one gate electrode structure 108 per two channel regions 116a and 116b in each transistor 110 in FIG. 1B; [0041, 48, 79]).
Regarding Claim 3, Yang-182 teaches the vertical dynamic random access memory (DRAM) cell of claim 1, further comprising a first dielectric layer extending from a first end a word line trench to a second end of the word line trench along a first side (gate dielectric material 112 along the side of line 136 facing 116a, running the length of the line, in FIG. 1 B; [0044, 48, 63]), wherein the second end is opposite the first end, and a second dielectric layer extending from the first end of the word line trench to the second end of the word line trench along a second side, wherein the second side is opposite the first side. ( 112 along the opposite side of line 136, facing 116b, in FIG. 1 B; [0063]).
Regarding Claim 10, Yang-182 teaches the vertical cell dynamic random-access memory (DRAM) array (microelectronic device structure 100, transistors 110 in rows and columns, in FIGS. 1A and 1B; memory device 400 of DRAM cells 402 in FIG. 4; [0031, 66, 89, 91]), comprising:
a first vertical dynamic random access memory cell (a first transistor 110, with 116a, 116b and 108, in FIG. 1B; [0034, 91]) disposed adjacent to a second vertical dynamic random access memory cell (the neighboring transistor 110 in the X-direction in FIG. 1B; [0051, 81]), wherein the first vertical dynamic random access memory cell and the second vertical dynamic random access memory cell ([0034]) comprise:
a bit line arranged in a first horizontal direction (line 104 in the X-direction under both transistors 110 in FIG. 1A; [0032]),
a first channel (116a of each transistor 110 in FIG. 1B; [0034, 37]),
a second channel (116b), and
a word line arranged in a second horizontal direction (y-direction) between the first channel and the second channel (each transistor's line 136 in the Y-direction, its 108
between its 116a and 116b, in FIG. 1B; [0034), [0048], [0051]),
wherein the first channel and the second channel extend in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction (Z-direction against X and Y in FIG. 1A; [0031, 34, 87]) such that the bit line intersects with a source/drain region of the first channel and the second channel ( 116a and 116b of each transistor 110 on its lower conductive contact 105, which stands on line 104, in FIG. 1A; [0035, 37, 47)), and the word line intersects with a gate region of the first channel and second channel (108 around 116a and 116b through 112 in FIG. 1B; [0041, 44, 63]); and an electrical isolation between the first vertical dynamic random access memory cell and the second vertical dynamic random access memory cell (isolation region 122 within opening 120, of passivation material 124, dielectric material 126 and air gaps 128, between neighboring transistors 110 in FIG. 1B; [0051, 52, 81]).
Regarding Claim 11, Yang-182 teaches the vertical cell dynamic random-access memory (DRAM) array of claim 10, wherein the first vertical dynamic random access memory cell and the second vertical dynamic random access memory cell each comprise only one word line for every two channels (one 108 per two channel regions in each transistor 110 of the array, the transistors in rows and columns, in FIGS. 1A and 1B; [0031, 41, 79]).
Regarding Claim 12, Yang-182 teaches the vertical cell dynamic random-access memory (DRAM) array according to claim 10, further comprising a third vertical dynamic random access memory cell adjacent to the second vertical dynamic random access memory cell (a third transistor 110 next along the same row in FIG. 1B; [0031]),
wherein an electrical isolation is disposed between the second vertical dynamic random access memory cell and the third vertical dynamic random access memory cell, and wherein the third vertical dynamic random access memory cell comprises a shared word line between two adjacent channels (the third transistor's 108, provided by a line 136, between its 116a and 116b in FIG. 1B; [0034, 48, 79]).
Regarding Claim 13, Yang-182 teaches the vertical cell dynamic random-access memory (DRAM) array according to claim 10, wherein electrical isolation comprises one or more dielectric materials, an air gap, or a combination thereof (isolation region 122 of passivation material 124, dielectric material 126 and air gaps 128, singly or in combination, in FIG. 1B; [0051, 52]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yang-182 (US # 20210351182) in view of Faul-870 (US # 20080308870) and further in view of Kang-422 (US # 20170125422).
Regarding Claim 4, Yang-182 teaches the vertical dynamic random-access memory (DRAM) cell of claim 3, further comprising wherein the first dielectric layer is formed from a material (112 along the side facing 116a, of silicon dioxide, in FIG. IB; [0044], [0045], [0063]) having a first work function, and wherein the second dielectric layer is fanned from a material (the same material 112 along the opposite side, facing 116b, in FIG. 1B; [0063]) having a second work function,
Although Yang-182 discloses much of the claimed invention, it does not explicitly teach the wherein the first work function is different than the second work function.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Faul-870 is in the same or analogous field, and it teaches first and second insulator structures 524 and 526 on the two opposite sides of the gate, each carrying a polar insulator layer 524a, 526a whose aligned dipoles act as a local bias of the gate and shift its effective work function at that side (FIG. 4C; [0060], [0061 ], [0062]); it teaches that the insulator structures on the two sides may be made asymmetric, both by asymmetric patterning ([0049]) and by forming one thinner than the other or from a different layer ([0056]); it teaches a buried gate whose two opposite lateral sections 485a and 485b are of different materials having different work functions (FIG. 40; [0053]); and it places such a transistor in a DRAM cell as access transistor 642 with storage capacitor 643 (FIG. 6; [0063]).
Furthermore, Kang-422 teaches which dielectric materials produce which shift within one buried word line: first work function adjustment liner 310, of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide or magnesium oxide, between gate dielectric layer 106 and the gate electrode, forming a dipole that raises the work function and thereby sets the threshold voltage (FIG. 4; [0068, 69, 70]); and second work function adjustment liner 311, of yttrium oxide, lanthanum oxide, germanium oxide, lutetium oxide or strontium oxide, forming a dipole that lowers it ([0071, 72, 74]); both within buried gate structure 300G of the access transistor of DRAM memory cell 500, which has bit line BL and memory element M (FIG. 9; [0066, 139, 141]).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have forn1ed the dielectric layer along the first side of the word line of Yang-182 from one of the work-function-raising liner materials of Kang-422 and the dielectric layer along the second, opposite side from one of its work-function-lowering liner materials, so that the first dielectric layer is formed from a material having a first work function and the second dielectric layer from a material having a second, different work function. Specifically, the modification suggested by Faul-870 and Kang-422 would be to employ a first and second dielectric layer with corresponding work functions wherein the first work function is different than the second work function. The rationale is that Faul-870 teaches that the insulator structures at the two opposite sides of a buried gate may be made asymmetric ([0049, 56]) and that a dipole insulator layer at such a side shifts the effective work function there ([0060-62]), and because Kang-422 teaches that the threshold voltage of a buried word line DRAM cell is set by the choice of such a liner ([0069, 75]), so that choosing the two liners independently sets the threshold voltage at each of the two channel regions of Yang-182 independently.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yang-182 (US # 20210351182) in view of Thies-587 (US # 20060113587).
Regarding Claim 14, although Yang-182 discloses much of the claimed invention, it does not explicitly teach the vertical cell dynamic random-access memory (DRAM) array according to claim 10, further comprising a substrate layer disposed between the bit line and the source/drain region of the first channel and the second channel.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Thies-587 is in the same or analogous field, and it teaches, in a transistor array having vertical channel access transistors in substrate pillars with buried bit lines and buried word lines, a body contact region of the second conductivity type adjacent the respective first doped region, separating that doped region from the adjacent bit line and extending from the channel region to the bulk section of the substrate ([0023]).
Thies-587 teaches a transistor array for semiconductor memory devices having vertical channel access transistors 71 and buried bit lines 2 and buried word lines 41 ([0001]; FIGS. 1B and 1C; [0100]), in which each access transistor 71 is formed in a substrate pillar 16 that extends outwardly from bulk section 15 of substrate 1, substrate 1 being single crystalline silicon (FIG. 1B, 16 above 15; [0062, 77, 93]), and each bit line 2, of metal 22 on barrier liner 21, lies in a bit line trench 20 below the pillar level, separated from substrate 1 by bottom insulating liner 31 (FIG. 1B, 2 and 31; [0066], [0067]). Each pillar 16 forms an active area 6 comprising a first doped region 61 of a first conductivity type in a bottom region of the pillar, adjacent the single sided bit line contact 3 by which bit line 2 is coupled to that active area (FIG. 1B, 61 beside 3 and 2; [0093], [0094]; claim 2), a second doped region 62 of the first conductivity type in the upper section of the pillar (FIG. 1B, 62; [0023]; claim 2), and a channel region 63 separating them, along which word lines 41 are disposed on gate dielectric 44 (FIG. 1B, 63 and 41; [0023, 95]; claim 2), the first conductivity type being n-conducting (claim 4). Each active area 6 further comprises a body contact region 64 of the second conductivity type, and therefore p-type, formed adjacent the respective first doped region 61 as a residual portion of a buried well layer of the second conductivity type in substrate 1 at the depth of bit lines 2, which the dopant forming region 61 has contradoped elsewhere (FIG. 1B, 64 beside 61; [0094]; [0153]; claim 3). Body contact region 64 separates first doped region 61 from the adjacent bit line 2 and extends from channel region 63 to bulk section 15 of substrate 1 (FIG. 1B, 64 between 61 and 2 and continuous with 15; [0023, 94]). Thies-587 teaches that, in a vertical channel access transistor array, separation of the channel region from the bulk section of the substrate causes an accumulation of minority charge carriers in the channel region that deteriorates the cell characteristics ([0018-19]), and that each body contact region connects the channel region of the respective active area to the bulk section of the semiconductor substrate, whereby an accumulation of minority charge carriers in the channel region is avoided and cell performance is enhanced ([0024]; claim 3).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have interposed a doped semiconductor body contact region of the kind taught by Thies-587 (body contact region 64 in FIG. 1B; [0094]) between first conductive line 104 and lower conductive contact 105 of Yang-182, so as to provide a substrate layer disposed between the bit line and the source/drain region of the first and second channels, because the first channel region 116a and the second channel region 116b of Yang-182 may be polysilicon ([0038]) and stand on lower conductive contact 105 over first conductive line 104 (FIG. 1A; [0035, 37]), so that they are electrically isolated from the substrate, and because Thies-587 teaches that a body contact region 64 so placed connects channel region 63 to bulk section 15 of substrate 1, whereby an accumulation of minority charge carriers in the channel region is avoided and cell performance is enhanced ([0018-19, 24]).
Allowable Subject Matter
Claim 5-9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 5, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including wherein the first side is adjacent to the first channel and the second side is adjacent to the second channel, wherein the first channel comprises a n-MOS channel and the second channel comprises a p-MOS channel.
Claims 6-9 depend on claim 5 and inherit the allowable subject matter.
Conclusion
Pertinent prior art:
US # 20200111916
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
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