Prosecution Insights
Last updated: October 01, 2026
Application No. 18/733,103

SEMICONDUCTOR STRUCTURE HAVING A MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§103§112
Filed
Jun 04, 2024
Examiner
MOJADDEDI, OMAR F
Art Unit
Tech Center
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
481 granted / 538 resolved
+29.4% vs TC avg
Moderate +10% lift
Without
With
+10.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
62 currently pending
Career history
579
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
53.8%
+13.8% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 538 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Status of Claims 1. Applicant's submittal of claims 1-10 in the “Claims” filed on 06/04/2024 is acknowledged and entered by the Examiner. This office action considers claims 1-10 pending for prosecution. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 2 Claims 7-8 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding Claim 7, the instant claim recites limitations in view of intervening claims 6, 5, 4, 3, and 2, and the parent device claim 1, wherein the metes and bounds of the claimed method are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “wherein the seal layer includes a linear layer and a planar layer, wherein the linear layer is disposed over the spacer structure, a horizontal portion of the second spacer dielectric layer, the dielectric layer and the sixth dielectric layer, and the planar layer is disposed over the linear layer” (Claim 7; emphasis added). The claim is indefinite because of the following: i) The claim is indefinite because “wherein the seal layer includes a linear layer and a planar layer, wherein the linear layer is disposed over the spacer structure, a horizontal portion of the second spacer dielectric layer, the dielectric layer and the sixth dielectric layer, and the planar layer is disposed over the linear layer” (Claim 7) lacks proper antecedent basis. The is no mention of “a dielectric layer” in claims 1-7. Therefore, the limitation of “wherein the seal layer includes a linear layer and a planar layer, wherein the linear layer is disposed over the spacer structure, a horizontal portion of the second spacer dielectric layer, the dielectric layer and the sixth dielectric layer, and the planar layer is disposed over the linear layer” (Claim 7) is indefinite and unclear. The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention. Regarding Claim 8, it is rejected under 112(b) because of their dependency status from claim 7. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. 3. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20220102352 A1; hereinafter Lee). Regarding claim 1, Lee teaches a semiconductor structure (see the entire document, specifically Fig. 1+; [0009+], and as cited below), comprising: a data storage unit (DSP1; Fig. 17C; [0166]) disposed in a first dielectric layer (ML1; Fig. 17C; [0154]); a word line (WL1a; Fig. 17C; [0166]) disposed in a second dielectric layer ({150, 151, 153, 155}; Fig. 17C; [0156-0160]) over the first dielectric layer (ML1; Fig. 17C; [0154]); an array of conductive pads (PADa; Fig. 17C; [0166]) disposed over the word line (WL1a; Fig. 17C; [0166]) and the second dielectric layer ({150, 151, 153, 155}; Fig. 17C; [0156-0160]); a bit line (164; Fig. 17C; [0164-0166]) disposed over the conductive pads (PADa; Fig. 17C; [0166]); a third dielectric layer (160; Fig. 17C; [0164]) disposed over the second dielectric layer ({150, 151, 153, 155}; Fig. 17C; [0156-0160]); a fourth dielectric layer (171; Fig. 17C; in view of [0160] in view of 151, where 151 is an insulating layer) disposed over the third dielectric layer (160; Fig. 17C; [0164]); Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. 4. Claims 2-10 are rejected under 35 U.S.C.103 as being unpatentable over Lee et al. (US 20220102352 A1; hereinafter Lee), in view of Xiao et al. (US 20250081437 A1; hereinafter Xiao, using the foreign priority date of 11/11/2022; Google Translation attached). Regarding claim 2, Lee teaches all of the features of claim 1. But, Lee does not expressly disclose further comprising a spacer structure disposed on sidewalls of the bit line, wherein the spacer structure includes a second air gap. However, in the analogous art, Xiao teaches a structure of a semiconductor structure ([Abstract]), wherein (Fig. 1A+; [0005+]) a second isolation layer (180; Fig. 8; [0029-0031]) between sidewalls of a bit line contact structure (161; Fig. 8; [0069]), where second isolation layer (180; Fig. 8; [0029-0031]) comprises an air gap (270; Fig. 8; [0031]), where the air gap (270; Fig. 8; [0031]) improves the reliability of the semiconductor structure. It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Xiao’s second isolation layer with air gaps into Lee/s device, and thereby, modified Lee’s (by Xiao) device will have further comprising a spacer structure (Xiao 180; Fig. 8; [0029-0031]) disposed on sidewalls of the bit line (Lee 164; Fig. 17C; [0164-0166]), wherein the spacer structure (Xiao 180; Fig. 8; [0029-0031]) includes a second air gap (Xiao 270; Fig. 8; [0029-0031]). The ordinary artisan would have been motivated to modify Costrini in the manner set forth above, at least, because this inclusion provides a second isolation layer comprising an an air gap, where the air gap improves the reliability of the semiconductor structure (Xiao [0031]). Regarding claim 3, modified Lee (by Xiao) teaches all of the features of claim 2. Modified Lee (by Xiao) further teaches wherein the second air gap (Xiao 270; Fig. 8; [0029-0031]) is sandwiched by a first spacer dielectric layer (Xiao left wall of 180 on left side of 270; Fig. 8; [0029-0031]) and a vertical portion of a second spacer dielectric layer (Xiao right wall of 180 on right side of 270; Fig. 8; [0029-0031]), and the second air gap (Xiao 270; Fig. 8; [0029-0031]) is sealed by a seal layer (Xiao 170; Fig. 8; [0028-0031]). Regarding claim 4, modified Lee (by Xiao) teaches all of the features of claim 3. Modified Lee (by Xiao) further teaches wherein the second air gap (Xiao 270; Fig. 8; [0029-0031]) (see below for “is formed by disposing a spacer layer in a first air gap between”) the first spacer dielectric layer (Xiao left wall of 180 on left side of 270; Fig. 8; [0029-0031]) and the second spacer dielectric layer (Xiao right wall of 180 on right side of 270; Fig. 8; [0029-0031]). In reference to the language in claim 4 referring to “wherein the second air gap is formed by disposing a spacer layer in a first air gap between the first spacer dielectric layer and the second spacer dielectric layer”, it is important to note that “Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Accordingly the limitation "wherein the second air gap is formed by disposing a spacer layer in a first air gap between the first spacer dielectric layer and the second spacer dielectric layer" is not patentable over prior art as the structure of the prior art cannot be differentiate from the structural limitation as claimed. Therefore, in reference to the language in claim 4 referring to wherein the second air gap is formed by disposing a spacer layer in a first air gap between the first spacer dielectric layer and the second spacer dielectric layer, it is noted that modified Lee (by Xiao) teaches all the structural elements in claim 4 according to the instant invention and that wherein the second air gap is formed by disposing a spacer layer in a first air gap between the first spacer dielectric layer and the second spacer dielectric layer does not affect the structure of the final device. Regarding claim 5, modified Lee (by Xiao) teaches all of the features of claim 4. Modified Lee (by Xiao) further teaches wherein (see below for “the first air gap is formed by removing a sacrificial layer disposed between”) (see rejection of claim 4, above) the first spacer dielectric layer (Xiao left wall of 180 on left side of 270; Fig. 8; [0029-0031]) and the second spacer dielectric layer (Xiao right wall of 180 on right side of 270; Fig. 8; [0029-0031]). In reference to the language in claim 5 referring to “wherein the first air gap is formed by removing a sacrificial layer disposed between the first spacer dielectric layer and the second spacer dielectric layer”, it is important to note that “Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Accordingly the limitation "wherein the first air gap is formed by removing a sacrificial layer disposed between the first spacer dielectric layer and the second spacer dielectric layer" is not patentable over prior art as the structure of the prior art cannot be differentiate from the structural limitation as claimed (see also rejection of claim 4, above). . Therefore, in reference to the language in claim 5 referring to wherein the first air gap is formed by removing a sacrificial layer disposed between the first spacer dielectric layer and the second spacer dielectric layer, it is noted that modified Lee (by Xiao) teaches all the structural elements in claim 5 according to the instant invention and that wherein the first air gap is formed by removing a sacrificial layer disposed between the first spacer dielectric layer and the second spacer dielectric layer does not affect the structure of the final device (see also rejection of claim 4, above). Regarding claim 6, modified Lee (by Xiao) teaches all of the features of claim 5. Modified Lee (by Xiao) further comprising a fifth dielectric layer (Lee SIPb; Fig. 17C; in view of [0167]) disposed on the bit line (Lee 164; Fig. 17C; [0164-0166]) disposed on the bit line (Lee 164; Fig. 17C; [0164-0166]), and disposed over the third dielectric layer (Lee 160; Fig. 17C; [0164]) and the fourth dielectric layer (Lee 171; Fig. 17C; in view of [0160] in view of 151, where 151 is an insulating layer); and a sixth dielectric layer (175; Fig. 17C; in view of [0160] in view of 155, where 155 is an insulating layer) disposed between a pair of the fifth dielectric layers (Lee SIPb; Fig. 17C; in view of [0167]) disposed on the bit line (Lee 164; Fig. 17C; [0164-0166]) over the third dielectric layer (Lee 160; Fig. 17C; [0164]) and the fourth dielectric layer (Lee 171; Fig. 17C; in view of [0160] in view of 151, where 151 is an insulating layer). Regarding claim 7, modified Lee (by Xiao) teaches all of the features of claim 6. Modified Lee (by Xiao) further teaches wherein the seal layer (Xiao 170; Fig. 8; [0028-0031]) includes a linear layer (Xiao side portion 170; see Fig. 8; [0028-0031]) and a planar layer (Xiao top portion 170; see Fig. 8; [0028-0031]), wherein the linear layer (Xiao side portions 170; see Fig. 8; [0028-0031]) is disposed over the spacer structure (Xiao 180; Fig. 8; [0029-0031]), a horizontal portion of the second spacer dielectric layer (Xiao right wall of 180 on right side of 270; Fig. 8; [0029-0031]), the dielectric layer (see section 2, above; 112(b) rejection) and the sixth dielectric layer (Lee 175; Fig. 17C; in view of [0160] in view of 155, where 155 is an insulating layer), and the planar layer (Xiao top portion 170; see Fig. 8; [0028-0031]) is disposed over the linear layer (Xiao side portion 170; see Fig. 8; [0028-0031]). Regarding claim 8, modified Lee (by Xiao) teaches all of the features of claim 7. Modified Lee (by Xiao) further comprising a conductive via (Xiao 130; Fig. 8; [0079-0089]) extending through the seal layer (Xiao 170; Fig. 8; [0028-0031]) and the fifth dielectric layer (Lee SIPb; Fig. 17C; in view of [0167]), wherein the conductive via (Xiao 130; Fig. 8; [0079-0089]) is connected to a conductive pad (Xiao 154; Fig. 8; [0081-0082]) over the third (Lee 160; Fig. 17C; [0164]) and the fourth dielectric layer (Lee 171; Fig. 17C; in view of [0160] in view of 151, where 151 is an insulating layer). Regarding claim 9, modified Lee (by Xiao) teaches all of the features of claim 4. Modified Lee (by Xiao) further teaches wherein a width of the second air gap (Xiao 270; Fig. 8; [0029-0031]) (see below for “is less than a width of the first air gap”) (see rejection of claim 4, above). In reference to the language in claim 9 referring to “wherein a width of the second air gap is less than a width of the first air gap”, it is important to note that “Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Accordingly the limitation " wherein a width of the second air gap is less than a width of the first air gap " is not patentable over prior art as the structure of the prior art cannot be differentiate from the structural limitation as claimed (see also rejection of claim 4, above). Therefore, in reference to the language in claim 9 referring to wherein a width of the second air gap is less than a width of the first air gap, it is noted that modified Lee (by Xiao) teaches all the structural elements in claim 9 according to the instant invention and that wherein a width of the second air gap is less than a width of the first air gap does not affect the structure of the final device (see also rejection of claim 4, above). Regarding claim 10, modified Lee (by Xiao) teaches all of the features of claim 9. Modified Lee (by Xiao) further teaches wherein (see below for “the spacer layer is made of a material same as”) a material of the first dielectric layer (ML1; Fig. 17C; [0154]) and the second dielectric layer ({150, 151, 153, 155}; Fig. 17C; [0156-0160]). In reference to the language in claim 10 referring to “wherein the spacer layer is made of a material same as a material of the first dielectric layer and the second dielectric layer”, it is important to note that “Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Accordingly the limitation " wherein the spacer layer is made of a material same as a material of the first dielectric layer and the second dielectric layer " is not patentable over prior art as the structure of the prior art cannot be differentiate from the structural limitation as claimed (see also rejection of claim 4, above). Therefore, in reference to the language in claim 10 referring to wherein the spacer layer is made of a material same as a material of the first dielectric layer and the second dielectric layer, it is noted that modified Lee (by Xiao) teaches all the structural elements in claim 10 according to the instant invention and that wherein the spacer layer is made of a material same as a material of the first dielectric layer and the second dielectric layer does not affect the structure of the final device (see also rejection of claim 4, above). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado, can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /OMAR F MOJADDEDI/Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jun 04, 2024
Application Filed
Sep 24, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+10.4%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 538 resolved cases by this examiner. Grant probability derived from career allowance rate.

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