Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 63 and 86 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In independent claim 63, lines 9-10 and 12-13, the use of the phrase “another side of third power package side” and “another side of fourth power package side” renders the claim unclear because it is not clear how a given side can also have an additional side. Clarification is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 6-7, 12-13, 15-17, 19-24, 32, 55, 58, 63, and 86 is/are rejected under 35 U.S.C. 103 as being unpatentable over McPherson et al., US 2023/0142930 in view of Chen, US 2019/0229043.
McPherson et al. shows the invention as claimed including a power package 10 comprising:
An assembly comprising a first power package side, a second power package side, a third power package side, and fourth power package side (power module 10 in figs. 2-3 has four sides—see paragraph 0067);
First power terminals arranged at the first power package side (power terminals V+ and V- on first side of module—see paragraphs 0069-0071);
Second power terminals arranged at the second power package side (power terminals U/V/W shown on second side of power module—see paragraphs 0069-0071);
First signal terminals (see signal terminals G2/K2 and G4/K4, for example, in fig. 10 and paragraph 0076);
Second signal terminals (see signal terminals G1/K1 and G3/K3, for example), and wherein a location of the first power terminals at the first power package side is symmetrical with respect to a location of the second power terminals at the second power package side (see, for example, fig. 8 and its description which shows the symmetrical arrangement.
McPherson et al. does not expressly disclose where the first and second signal terminals are arranged at the third and fourth package side. Chen discloses a power package whereby signal terminals 12 are formed symmetrically on all four sides of the package (see, for example, fig. 5 and paragraphs 0034-0046). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the primary reference of McPherson et al. so as to form signal terminals on all sides of the package symmetrically including a third and fourth package side because in such a way adequate and excellent design of the power package can be facilitated.
Concerning dependent claim 2, note that McPherson et al. discloses further comprising a single power die, wherein the power package is configured as a power discrete package 10 (see, for example, figs. 15 and 21).
Regarding dependent claim 3, note that McPherson et al. discloses a single power die but fails to disclose two power dies, wherein the power package is configured as a power discrete package implementing the two power dies. However, a prima facie case of obviousness still exists because duplication of parts has been held to have been obvious. Additionally, duplicating working parts of a device would have been obvious to one of ordinary skill in the art at the time the invention was filed.
With respect to dependent claim 4, note that McPherson et al. discloses wherein the first power package side and the second power package side are opposing power package sides (first side with power terminals V+/V- is opposite of second side with power terminals U/V/W (see fig. 10 and paragraphs 0069-0071); and wherein the third power package side and the fourth power package side are opposing power package sides (third power module side with substrate S is opposite of fourth side---see fig. 10 and paragraph 0069).
As to dependent claim 6, note that McPherson et al. discloses wherein the first and second terminals comprise one or more of kelvin terminals (for example K2/K4/K6), kelvin drain terminals, gate terminals, and/or sensor terminals (see paragraph 0065, 0099, and fig. 21).
Regarding dependent claim 7, note that McPherson et al. discloses an arrangement configured to provide topside cooling (note that the thermal pad 14 shown in fig. 16 and described in paragraph 0067 facilitates the transfer of heat from the power module 10 to ambient).
As to dependent claim 12, McPherson et al. discloses the power package further comprising a top substrate S (fig. 19 and paragraph 0095) and at least one power die arranged under the top substrate (see figs. 19 and 21 and paragraphs 0095-0099).
Concerning dependent claim 13, McPherson et al. discloses wherein the top substrate and the at least one power die are configured in an arrangement configured to provide topside cooling (see fig. 16 and paragraphs 0067 and 0099).
Regarding dependent claim 15, note that McPherson et al. discloses further comprising a source interconnect configured to be electrically connected to a source of at least one power die (note that the signals flow from the source pad and source Kelvin pad of transistors Q1-Q6 over bond wires to the signal terminal K1-K6---see fig. 21 and paragraph 0099).
With respect to dependent claim 16, McPherson et al. discloses wherein the source interconnect is connected to at least one of the first power terminals and/or at least one of the second power terminals (U/V/W power terminals are coupled using bond wires to the source pads; power flows through power terminal V+ down to device pad of the substrate through bond wires-see paragraph 00095).
As to dependent claim 17, McPherson et al. discloses the power package further comprising risers arranged on the at least one power die, wherein the risers are configured to be electrically connected with the source interconnect (see, for example, paragraph 0095 and figs. 16 and 20-21).
With respect to dependent claim 19, note that McPherson et al. discloses wherein one of the first power terminals and the second power terminals are configured to connect to the top substrate (power flows through power terminal V+ down to device pad of the substrate S through power bond wires—see fig. 16 and paragraph 0095).
As to dependent claim 20, McPherson et al. discloses wherein another one of the first and second power terminals are configured to connect to at least one power die (see figs. 20-21 which disclose power terminals U/V/W connected to transistors Q1-Q6 , the signals flowing through the gate pad GP of transistors Q1-Q6--see paragraphs 0095 and 0099).
Regarding dependent claim 21, note that McPherson et al. discloses an insulation layer arranged on the top substrate (thermal pad insulation layer 14 arranged on substrate S---see fig. 16 and paragraph 0082), wherein at least one of the first and second signal terminals are arranged on the insulation layer (see signal terminals G1/K1 arranged on the thermal pad 14 on fig. 8).
Concerning dependent claim 22, McPherson et al. discloses at least one signal interconnect, wherein an implementation of the at least one signal interconnect is connected to at least two of the first signal terminals (signals flow from source pad and source Kelvin pad of transistors Q1-Q6 over bond wires/source interconnect to the signal terminal G2/K2---see fig. 21 and paragraph 0099); and wherein an implementation of the at least one signal interconnect is connected to at least two of the second signal terminals (signals flow from the source pad and the source Kelvin pad of transistors Q1-Q6 over bond wires to the signal terminal G1/K1 (see fig. 21 and paragraph 0099).
As to dependent claim 23, McPherson et al. discloses wherein the first power terminals comprise a first power and a second power terminal V+ and V- (see fig. 10 and paragraphs 0069 and 0071) and the second power terminals comprise a first, second, and third power terminal (U/V/W—also, see fig. 10 and paragraphs 0069 and 0071). However, McPherson et al. does not expressly disclose the first and second power terminals each having four power terminals. However, a prima facie case of obviousness still exists because duplication of parts has been held to have been obvious. Additionally, duplicating working parts of a device would have been obvious to one of ordinary skill in the art at the time the invention was filed.
Regarding dependent claims 24, 55, and 86, note that McPherson et al. discloses wherein the configuration of the at least one implementation of the power package being configured, structured, arranged, and/or implemented such that the configuration implements a standalone configuration, a paralleled configuration, a common-source configuration, a common-drain configuration, a common-source bidirectional configuration, and/or a common-drain bidirectional configuration (see, for example, paragraphs 0063-0065 and 0100).
As to independent claim 32, McPherson et al. shows the invention as claimed including a power package 10 comprising:
An assembly comprising a first power package side, a second power package side, a third power package side, and fourth power package side (power module 10 in figs. 2-3 has four sides—see paragraph 0067);
First power terminals arranged at the first power package side (power terminals V+ and V- on first side of module—see paragraphs 0069-0071);
Second power terminals arranged at the second power package side (power terminals U/V/W shown on second side of power module—see paragraphs 0069-0071);
First signal terminals (see signal terminals G2/K2 and G4/K4, for example, in fig. 10 and paragraph 0076); and
Second signal terminals (see signal terminals G1/K1 and G3/K3, for example),
McPherson et al. does not expressly disclose where the first and second signal terminals are arranged at the third and fourth package side and a location of the first signal terminals on third power package side is symmetrical with respect to a location of the second signal terminals on fourth power package side. Chen discloses a power package whereby signal terminals are formed on all four sides of the package. In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the primary reference of McPherson et al. so as to form signal terminals on all sides of the package including a third and fourth package side because in such a way an efficient design of a power package can be realized.
Regarding dependent claim 58, note that McPherson et al. modified by Chen discloses wherein a location of the first power terminals at the first power package side is symmetrical with respect to a location of the second power terminals at the second power package side.
Concerning independent claim 63, note that as best understood, the device of McPherson et al. modified by Chen discloses the claimed symmetric configuration.
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over McPherson et al., US 2023/0142930 in view of Chen, US 2019/0229043 as applied to claims 1-4, 6-7, 12-13, 15-17, 19-24, 32, 55, 58, 63, and 86 above, and further in view of Guerra et al., US 2004/0227476.
McPherson et al. and Chen are applied as above but do not expressly disclose further comprising an arrangement configured for surface mount implementations. Guerra et al. discloses configuring a power device for surface mount implementations (see, for example, paragraph 0009). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the power package device of McPherson et al. modified by Chen so as to be an arrangement configured for surface mount implementations because this is shown by Guerra et al. to be a conventional implementation of a power based device.
As to dependent claim 18, McPherson et al. and Chen are applied as above but do not expressly disclose wherein the assembly comprises a configuration that is encapsulated in epoxy, overmolded, overmolded with epoxy, and/or potted, potted with a dielectric material. Guerra et al. discloses wherein a power assembly comprises a configuration that is encapsulated in epoxy, overmolded, overmolded with epoxy, and/or potted, potted with a dielectric material (see that package 170 is over-molded, see fig. 8A and paragraph 0009). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the power package of McPherson et al. modified by Chen so as to comprise the overmolded package as disclosed by Guerra et al. because this is shown to be a conventional means with which to encapsulate a power package device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hume et al., US Patent 6,414,389 discloses an LDMOS power package (see abstract), and Lee et al., US 2007/0246772 discloses a MOSFET power package (see abstract, lines 1-5).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
August 31, 2026
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