DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 2, 2026, has been entered.
Response to Amendment
Applicant’s amendment dated March 2, 2026, in which claims 1-20 were amended, has been entered.
Claim Objections
Claims 9 and 16 are objected to because of the following informalities:
The claimed reference character “semiconductor substrate (202)” should be changed to --semiconductor substrate (302)-- to be more accurate.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5, 13, and 18-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 5, 13, and 18, the disclosure based on the embodiment of Figs.12-18 indicates that the second metal liner [314] “includes at least one material selected from the group consisting of: cobalt (Co), ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), zinc (Zn), aluminum (Al), and manganese (Mn)” [Para.44]. The subject matter below in claims 5, 13, and 18, respectively,
wherein the second metal liner layer includes at least one material selected from the group consisting of: a Co nitride, a Co carbide, a Co hydride, a Ru nitride, a Ru carbide, a Ru-C-N, a Ru hydride complex, a Ta nitride, a Ta carbide, and a Ta hydride;
wherein the second metal liner layer includes at least one material selected from the group consisting of: a carbide-based metal structure, a nitride-based metal structure, and a hydride-based metal structure;
wherein the liner structure includes at least one material selected from the group consisting of: a carbide material, a nitride material, and a hydride material,
was not described.
Claim 19 is rejected due to its dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7, 9-10, 12, 14-17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (U.S. Pub. 2019/0355618) [Hereafter “Lin”].
Regarding claims 1-4, Lin [Figs.1-4] discloses a method of forming a semiconductor device, comprising:
forming a dielectric layer [18] over a conductive region [14; Paras.15-16] of a semiconductor substrate [12];
forming a recess [20] in the dielectric layer;
depositing, in the recess, a first metal liner layer [24] formed mainly of a first transition metal that is selected from the group consisting of transition metals from groups 4 to 9 of the periodic table [Para.17; cobalt (Co) or ruthenium (Ru)];
depositing, in the recess, a second metal liner layer [26] formed mainly of a second transition metal that is different from the first transition metal [Para.17; cobalt (Co) or ruthenium (Ru)], wherein the first metal liner layer and the second metal liner layer form a liner structure;
forming a metal layer [28] over the liner structure, wherein the liner structure and the metal layer [Para.17; copper (Cu)] have different compositions;
planarizing the metal layer to form an interconnect structure [34] [Figs.3-4]; and
performing a thermal treatment [30] while a top surface of the metal layer is exposed [Fig.3; Para.18];
wherein the first transition metal is selected from the group consisting of: cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and manganese (Mn), and the metal layer is formed mainly of copper (Cu) [Para.17];
(wherein) the second transition metal is selected from the group consisting of cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), zinc (Zn), aluminum (Al), and manganese (Mn);
wherein the metal layer [28] includes copper (Cu) [Para.17].
Regarding claims 6-7, Lin [Figs.1-4] discloses a method of forming a semiconductor device,
further comprising forming a barrier layer [22] in the recess before forming the first metal liner layer, wherein the barrier layer includes a nitride material [Para.17];
wherein an entirety of the liner structure is formed to directly contact each boundary of the interconnect structure [34].
Regarding claims 9-10, Lin [Figs.1-4] discloses a method of forming a semiconductor device, comprising:
forming an inter-metal dielectric (IMD) layer [18] over a semiconductor substrate (202) [12];
forming a cavity [20] in the IMD layer;
forming a liner structure in the cavity, wherein forming the liner structure includes:
depositing a first metal liner layer [24] formed mainly of a first transition metal that is selected from the group consisting of transition metals from groups 4 to 9 of the periodic table [Para.17; cobalt (Co) or ruthenium (Ru)]; and
depositing a second metal liner layer [26] formed mainly of a second transition metal that is different from the first transition metal [Para.17; cobalt (Co) or ruthenium (Ru)];
forming an interconnect structure over the liner structure in the cavity, the interconnect structure including a metal material [28] directly contacting the liner structure; and
performing a thermal treatment [30] while a top surface of the metal material is exposed;
wherein the first transition metal is selected from the group consisting of: cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and manganese (Mn).
Regarding claims 12, 14, and 15, Lin [Figs.1-4] discloses a method of forming a semiconductor device,
(wherein) the second transition metal is selected from the group consisting of cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), zinc (Zn), aluminum (Al), and manganese (Mn);
wherein forming the interconnect structure includes:
forming the metal material [28] over the liner structure to fill the cavity; and
planarizing the metal material to form the interconnect structure [34] [Figs.3-4];
further comprising performing an annealing process [30] after forming the liner structure [Figs.2-3].
Regarding claims 16-17 and 20, Lin [Figs.1-4] discloses a method of forming a semiconductor device, comprising:
forming an inter-metal dielectric (IMD) layer [18] over a semiconductor substrate (202) [12];
forming a recess [20] in the IMD layer;
depositing a barrier layer [22] in the recess;
forming a liner structure in the recess by depositing a first liner layer [24] formed mainly of a first transition metal that is selected from the group consisting of transition metals from groups 4 to 9 of the periodic table over the barrier layer, and depositing a second liner layer [26] formed mainly of a second transition metal that is different from the first transition metal [Para.17; cobalt (Co) or ruthenium (Ru)];
filling the recess with a metal material [28] over the liner structure, wherein the liner structure and the metal material have different compositions [Para.17];
planarizing the metal material to form an interconnect structure [34]; and
performing a thermal treatment [30] while a top surface of the metal material is exposed;
wherein the first transition metal is selected from the group consisting of: cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and manganese (Mn);
wherein an entirety of the liner structure is formed to directly contact each boundary of the interconnect structure [Fig.4].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (U.S. Pub. 2019/0355618) in view of Koschinsky et al. (U.S. Pub. 2017/0117179) [Hereafter “Koschinsky”].
Regarding claim 8, Lin fails to explicitly disclose forming a second dielectric layer. Lin [Para.21] discloses the top surface of interconnect structure [34] can be connected to other metal interconnections through subsequent forming steps. Koschinsky [Fig.5] discloses forming a second dielectric layer [104] over the interconnect structure [107-110]. It would have been obvious to include further comprising forming a second dielectric layer over the interconnect structure, after the thermal treatment is performed as claimed since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 11, Lin [Para.21] discloses the top surface of interconnect structure [34] can be connected to other metal interconnections through subsequent forming steps. Lin fails to explicitly disclose repeating the process and forming a second interconnect structure over the interconnect structure [34]. However, Koschinsky [Fig.5] discloses and makes obvious
the IMD layer [102] is a first IMD layer, the cavity [105] is a first cavity, the liner structure [106] is a first liner structure, and the interconnect structure [110] is a first interconnect structure; and
the method further comprises:
forming a second IMD layer [104] over the first interconnect structure;
forming a second cavity [111/112] in the second IMD layer;
forming a second liner structure [415] in the second cavity, wherein a bottom surface [117] of the second liner structure extends laterally beyond sidewalls of the first liner structure [106]; and
forming a second interconnect structure [502] in the second cavity over the second liner structure.
Forming multilayer interconnects is obvious and well-known in semiconductor manufacturing. It would have been obvious to provide the second interconnect structure as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/BAC H AU/Primary Examiner, Art Unit 2898