Prosecution Insights
Last updated: October 02, 2026
Application No. 18/733,512

SEMICONDUCTOR DEVICE INCLUDING LINER STRUCTURE

Final Rejection §103
Filed
Jun 04, 2024
Priority
Jun 25, 2020 — continuation of 12/027,419
Examiner
AU, BAC H
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
4 (Final)
81%
Grant Probability
Favorable
5-6
OA Rounds
1m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
684 granted / 845 resolved
+12.9% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
18 currently pending
Career history
867
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 845 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s amendment dated June 22, 2026, in which claims 1, 5, 9, 13, 16, 18, and 19 were amended, has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-7, 9-10, and 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (U.S. Pub. 2019/0355618) [Hereafter “Lin”] in view of Shaviv et al. (U.S. Pub. 2017/0200642) [Hereafter “Shaviv”]. Regarding claims 1-5, Lin [Figs.1-4] discloses a method of forming a semiconductor device, comprising: forming a dielectric layer [18] over a conductive region [14; Paras.15-16] of a semiconductor substrate [12]; forming a recess [20] in the dielectric layer; depositing, in the recess, a first metal liner layer [24] formed mainly of a first transition metal that is selected from the group consisting of transition metals from groups 4 to 9 of the periodic table [Para.17; cobalt (Co) or ruthenium (Ru)]; depositing, in the recess, a second metal liner layer [26] formed mainly of a second transition metal that is different from the first transition metal [Para.17; cobalt (Co) or ruthenium (Ru)], wherein the first metal liner layer and the second metal liner layer form a liner structure; forming a metal layer [28] over the liner structure, wherein the liner structure and the metal layer [Para.17; copper (Cu)] have different compositions; planarizing the metal layer to form an interconnect structure [34] [Figs.3-4]; and performing a thermal treatment [30] while a top surface of the metal layer is exposed [Fig.3; Para.18]; wherein the first transition metal is selected from the group consisting of: cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and manganese (Mn), and the metal layer is formed mainly of copper (Cu) [Para.17]; (wherein) the second transition metal is selected from the group consisting of cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), zinc (Zn), aluminum (Al), and manganese (Mn); wherein the metal layer [28] includes copper (Cu) [Para.17]; wherein the second metal liner [26] layer includes at least one material selected from the group consisting of: cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), zinc (Zn), aluminum (Al), and manganese (Mn). Lin fails to explicitly disclose performing a thermal treatment after planarizing the metal layer. However, Shaviv [Figs.1A-F] discloses a method of forming a semiconductor device, comprising performing a thermal treatment after planarizing the metal layer [32] [Fig.1E-F] [Para.75]. Shaviv [Para.67] also discloses performing a thermal treatment prior to planarizing the metal layer. Shaviv discloses and makes obvious a method comprising performing a thermal treatment after planarizing the metal layer. It would have been obvious to one of ordinary skill in the art at the time the invention was made to incorporate the teachings of Shaviv into the method of Lin to include performing a thermal treatment after planarizing the metal layer. The ordinary artisan would have been motivated to modify Lin in the manner set forth above for at least the purpose to promote crystal growth, to stabilize and lower the resistivity of the films, and to seal any remaining microvoids and seams [Shaviv; Para.75]. Regarding claims 6-7, Lin [Figs.1-4] discloses a method of forming a semiconductor device, further comprising forming a barrier layer [22] in the recess before forming the first metal liner layer, wherein the barrier layer includes a nitride material [Para.17]; wherein an entirety of the liner structure is formed to directly contact each boundary of the interconnect structure [34]. Regarding claims 9-10, Lin [Figs.1-4] discloses a method of forming a semiconductor device, comprising: forming an inter-metal dielectric (IMD) layer [18] over a semiconductor substrate (202) [12]; forming a cavity [20] in the IMD layer; forming a liner structure in the cavity, wherein forming the liner structure includes: depositing a first metal liner layer [24] formed mainly of a first transition metal that is selected from the group consisting of transition metals from groups 4 to 9 of the periodic table [Para.17; cobalt (Co) or ruthenium (Ru)]; and depositing a second metal liner layer [26] formed mainly of a second transition metal that is different from the first transition metal [Para.17; cobalt (Co) or ruthenium (Ru)]; forming an interconnect structure over the liner structure in the cavity, the interconnect structure including a metal material [28] directly contacting the liner structure; and performing a thermal treatment [30] while a top surface of the metal material is exposed; wherein the first transition metal is selected from the group consisting of: cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and manganese (Mn). Lin fails to explicitly disclose performing a thermal treatment after planarizing the metal layer. However, Shaviv [Figs.1A-F] discloses a method of forming a semiconductor device, comprising performing a thermal treatment after planarizing the metal layer [32] [Fig.1E-F] [Para.75]. Shaviv [Para.67] also discloses performing a thermal treatment prior to planarizing the metal layer. Shaviv discloses and makes obvious a method comprising performing a thermal treatment after planarizing the metal layer. It would have been obvious to one of ordinary skill in the art at the time the invention was made to incorporate the teachings of Shaviv into the method of Lin to include performing a thermal treatment after planarizing the metal layer. The ordinary artisan would have been motivated to modify Lin in the manner set forth above for at least the purpose to promote crystal growth, to stabilize and lower the resistivity of the films, and to seal any remaining microvoids and seams [Shaviv; Para.75]. Regarding claims 12-15, Lin [Figs.1-4] discloses a method of forming a semiconductor device, (wherein) the second transition metal is selected from the group consisting of cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), zinc (Zn), aluminum (Al), and manganese (Mn); wherein the second metal liner [26] layer includes at least one material selected from the group consisting of: cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), zinc (Zn), aluminum (Al), and manganese (Mn); wherein forming the interconnect structure includes: forming the metal material [28] over the liner structure to fill the cavity; and planarizing the metal material to form the interconnect structure [34] [Figs.3-4]; further comprising performing an annealing process [30] after forming the liner structure [Figs.2-3]. Regarding claim 16, Lin [Figs.1-4] discloses a method of forming a semiconductor device, comprising: forming an inter-metal dielectric (IMD) layer [18] over a semiconductor substrate (202) [12]; forming a recess [20] in the IMD layer; depositing a barrier layer [22] in the recess; forming a liner structure in the recess by depositing a first liner layer [24] formed mainly of a first transition metal that is selected from the group consisting of transition metals from groups 4 to 9 of the periodic table over the barrier layer, and depositing a second liner layer [26] formed mainly of a second transition metal that is different from the first transition metal [Para.17; cobalt (Co) or ruthenium (Ru)]; filling the recess with a metal material [28] over the liner structure, wherein the liner structure and the metal material have different compositions [Para.17]; planarizing the metal material to form an interconnect structure [34]; and performing a thermal treatment [30] while a top surface of the metal material is exposed. Lin fails to explicitly disclose performing a thermal treatment after planarizing the metal layer. However, Shaviv [Figs.1A-F] discloses a method of forming a semiconductor device, comprising performing a thermal treatment after planarizing the metal layer [32] [Fig.1E-F] [Para.75]. Shaviv [Para.67] also discloses performing a thermal treatment prior to planarizing the metal layer. Shaviv discloses and makes obvious a method comprising performing a thermal treatment after planarizing the metal layer. It would have been obvious to one of ordinary skill in the art at the time the invention was made to incorporate the teachings of Shaviv into the method of Lin to include performing a thermal treatment after planarizing the metal layer. The ordinary artisan would have been motivated to modify Lin in the manner set forth above for at least the purpose to promote crystal growth, to stabilize and lower the resistivity of the films, and to seal any remaining microvoids and seams [Shaviv; Para.75]. Regarding claims 17-20, Lin [Figs.1-4] discloses a method of forming a semiconductor device, comprising: wherein the first transition metal is selected from the group consisting of: cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and manganese (Mn); wherein the liner structure [24,26] includes at least one material selected from the group consisting of: cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), zinc (Zn), aluminum (Al), and manganese (Mn); wherein the second transition metal is selected from the group consisting of: cobalt (Co), ruthenium (Ru) [Para.17; cobalt (Co) or ruthenium (Ru)], titanium (Ti), tungsten (W), molybdenum (Mo), manganese (Mn), and tantalum (Ta); wherein an entirety of the liner structure is formed to directly contact each boundary of the interconnect structure [Fig.4]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (U.S. Pub. 2019/0355618) in view of Shaviv et al. (U.S. Pub. 2017/0200642), as applied above and further in view of Koschinsky et al. (U.S. Pub. 2017/0117179) [Hereafter “Koschinsky”]. Regarding claim 8, Lin fails to explicitly disclose forming a second dielectric layer. Lin [Para.21] discloses the top surface of interconnect structure [34] can be connected to other metal interconnections through subsequent forming steps. Koschinsky [Fig.5] discloses forming a second dielectric layer [104] over the interconnect structure [107-110]. It would have been obvious to include further comprising forming a second dielectric layer over the interconnect structure, after the thermal treatment is performed as claimed since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claim 11, Lin [Para.21] discloses the top surface of interconnect structure [34] can be connected to other metal interconnections through subsequent forming steps. Lin fails to explicitly disclose repeating the process and forming a second interconnect structure over the interconnect structure [34]. However, Koschinsky [Fig.5] discloses and makes obvious the IMD layer [102] is a first IMD layer, the cavity [105] is a first cavity, the liner structure [106] is a first liner structure, and the interconnect structure [110] is a first interconnect structure; and the method further comprises: forming a second IMD layer [104] over the first interconnect structure; forming a second cavity [111/112] in the second IMD layer; forming a second liner structure [415] in the second cavity, wherein a bottom surface [117] of the second liner structure extends laterally beyond sidewalls of the first liner structure [106]; and forming a second interconnect structure [502] in the second cavity over the second liner structure. Forming multilayer interconnects is obvious and well-known in semiconductor manufacturing. It would have been obvious to provide the second interconnect structure as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007). Response to Arguments Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made Final. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BAC H AU/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Show 4 earlier events
Feb 18, 2026
Applicant Interview (Telephonic)
Feb 19, 2026
Examiner Interview Summary
Feb 24, 2026
Response after Non-Final Action
Mar 02, 2026
Request for Continued Examination
Mar 06, 2026
Response after Non-Final Action
Mar 23, 2026
Non-Final Rejection mailed — §103
Jun 22, 2026
Response Filed
Aug 27, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
81%
Grant Probability
92%
With Interview (+11.0%)
2y 5m (~1m remaining)
Median Time to Grant
High
PTA Risk
Based on 845 resolved cases by this examiner. Grant probability derived from career allowance rate.

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