DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/4/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR MEMORY STRUCTURE AND FORMING METHOD THEREOF.
Claims Status
Claims 1-20 are currently pending and being examined.
Claim Objections
Claim 3 is objected to because of the following informalities: the grammatical error “the first source/drain” in line 1 is believed intended to read as “the first source/drain contact”. Appropriate correction is required.
Claims 12-17 are objected to because of the following informalities: the claim 12 grammatical error “comprises a first conductive pattern extends in a second direction” in line 12 is believed intended to read as “comprises a first conductive pattern extending in a second direction”. Appropriate correction is required.
Claims 14 is objected to because of the following informalities: the grammatical error “the first and second conductive pattern” in line 2 is believed intended to read as “comprises a first and second conductive patterns”. Appropriate correction is required.
Claims 17 is objected to because of the following informalities: the grammatical error “forming a gate structures” in line 3 is believed intended to read as “forming gate structures”. Appropriate correction is required.
In Re claims 13 and 15-16, they are objected to due to their dependence from claim 12.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-8, 10-11; and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US 2023/0052883 A1).
Re claim 1, Liaw discloses in FIGS. 1A-1C, 2A, 2B, 4A, 4C and 4E a method, comprising:
forming a first static random access memory (SRAM) cell (101A/101B; [0021]-[0022]) over (on) a semiconductive substrate (12; [0020]; [0025] and [0058]);
forming a second SRAM cell (101C/101D; [0021]-[0022]) over the semiconductive substrate (12) and adjacent to (below) the first SRAM cell (101A/101B);
forming a first source/drain contact (left 120B in FIG. 2A; [0035]) across the first (101A/101B) and second (101C/101D) SRAM cells, wherein the first source/drain contact (120B) is electrically coupled ([0035]) to a source/drain region (114N; [0034]-[0035]) of a first pass-gate transistor (PG-1 of 101A; [0034]) in the first SRAM cell (101A/101B) and a source/drain region (114N; [0034]-[0035]) of a second pass-gate transistor (PG-1 of 101C; [0034]) in the second SRAM cell (101C/101D); and
forming a first source/drain contact via (left 126C; [0036]) over the first source/drain contact (left 120B).
Re claim 2, Liaw discloses the method of claim 1, wherein the first source/drain contact via (left 126C) extends along a longitudinal direction (X in FIG. 2A) of a gate electrode (left 130B; [0030]) of the first pass-gate transistor (PG-1 of 101A).
Re claim 4, Liaw discloses the method of claim 1, further comprising: forming a second source/drain contact (right 120B in FIG. 2A; [0035]) across the first (101A/101B) and second (101C/101D) SRAM cells, wherein the second source/drain contact (right 120B) is electrically coupled ([0035]) to a source/drain region (114N; [0034]-[0035]) of a third pass-gate transistor (PG-1 of 101B; [0034]) in the first SRAM cell (101A/101B) and a source/drain region (114N) of a fourth pass-gate transistor (PG-1 of 101D) in the second SRAM cell (101C/101D); and forming a second source/drain contact via (right 126C; [0036]) over the second source/drain contact (right 120B), wherein the second source/drain contact via (right 126C) extends along a longitudinal direction (X in FIG. 2A) of a gate electrode (right 130B; [0030]) of the third pass-gate transistor (PG-1 of 101B).
Re claim 6, Liaw discloses the method of claim 1, wherein forming the first SRAM cell (101A/101B) comprises: forming a semiconductor sheet (105 in FIG. 4E; [0026]-[0027]) over the semiconductive substrate (12); and forming a gate electrode (PG 134; [0029]) overlapping (GAA; [0034]) the semiconductor sheet (105).
Re claims 7-8, Liaw discloses the method of claim 1, wherein forming the first SRAM cell (101A/101B) comprises: forming a dielectric-based gate (left 138; [0029]) on a boundary (between PG-1 and PU-2) of the first SRAM cell (101A/101B); and wherein a longitudinal end (vertical edge) of the dielectric-based gate (left 138) abuts (physically touches) a longitudinal end (vertical edge) of a gate electrode (left 134) of the first pass-gate transistor (PG-1 of 101A).
Re claim 10, Liaw discloses the method of claim 1, wherein the first (101A/101B) and second (101C/101D) SRAM cells are arranged along a longitudinal direction (X in FIG. 2A) of a gate electrode (left 130B; [0030]) of the first pass-gate transistor (PG-1 of 101A).
Re claim 11, Liaw discloses the method of claim 10, further comprising: forming a word line (WL; [0033]) over the first (101A/101B) and second (101C/101D) SRAM cell, the word line (WL) extends along the longitudinal direction (X) of the gate electrode (left 130B) of the first pass-gate transistor (PG-1 of 101A).
Re claim 18, Liaw discloses in FIGS. 1A-1C, 2A, 2B, 4A, 4C and 4E a semiconductor structure, comprising:
a substrate (12; [0020]; [0025] and [0058]);
a first static random access memory (SRAM) cell (101B/101D; [0021]-[0022]) over the substrate (12) and comprising a first pull-down transistor (PD-2 of 101B; [0034]) and a second pull-down transistor (PD-2 of 101D; [0034]) sharing a first common source/drain region (114N; [0034]-[0035]);
a second SRAM cell (101A/101C; [0021]-[0022]) abutting (physically touching) the first SRAM cell (101B/101D) and comprising a third pull- down transistor (PD-2 of 101A; [0034]) and a fourth pull-down transistor (PD-2 of 101C; [0034]) sharing a second common source/drain region (114N; [0034]-[0035]); and
a first source/drain contact (120A in FIG. 2A; [0035]) over the first common source/drain region (114N) shared by the first (PD-2 of 101B) and second (PD-2 of 101D; [0034]) pull-down transistors, and the second common source/drain region (114N) shared by the third (PD-2 of 101A) and fourth pull-down transistors (PD-2 of 101C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of CHANG et al (US 2020/0343185 A1, hereafter Chang).
Re claim 3, Liaw discloses the method of claim 2.
But, fails to disclose wherein from a top view the first source/drain contact (left 126c) has a length-to-width ratio in a range from about 2 to about 5.
However,
Chang discloses in FIG. 4 rectangular contacts (256-266; [0032] and [0035]) with a length-to-width ratio in a range from about 2 to about 5 (2 to 3 times; [0032] and [0035]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Liaw, by using the dimensions disclosed by Chang, for forming the first source/drain contact to have a length-to-width ratio in a range from about 2 to about 5, for SRAM cells with reduce contact resistance (Chang; [0016]-[0017] and [0035]).
Claims 5; and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw.
Re claim 5, Liaw discloses the method of claim 4.
But, fails to disclose wherein the first (PG-1 of 101A) and third (PG-1 of 101B) pass-gate transistors share the same active region in the first SRAM cell (101A/101B).
However, these limitations would be rendered obvious through rearrangement of parts MPEP § 2144.04 VI. C.), since the first SRAM cell of Liaw comprise the same core elements (i.e. first-fourth pass-gate transistors and shared first (106 of 101A/101C) and second (106 of 101B/101D) active regions) in a different arrangement, which if rearranged would result in the first and third pass-gate transistors sharing the same active region in the first SRAM cell.
Re claims 19-20, Liaw discloses the semiconductor structure of claim 18, wherein the first SRAM cell (101B/101D) further comprises a first pass-gate transistor (PG-1 of 101B), the second SRAM cell (101A/101C) comprises a second pass-gate transistor (PG-1 of 101A); and wherein the first SRAM cell further comprises a third pass-gate transistor (PG-1 of 101D), the second SRAM cell further comprises a fourth pass-gate transistor (PG-1 of 101C).
But, fails to disclose and the semiconductor structure further comprises: a second source/drain contact over a source/drain region of the first pass-gate transistor in the first SRAM cell and a source/drain region of the second pass-gate transistor in the second SRAM cell; and the semiconductor structure further comprises: a third source/drain contact over a source/drain region of the third pass-gate transistor in the first SRAM cell and a source/drain region of the fourth pass-gate transistor in the second SRAM cell.
However, these limitations would be rendered obvious through rearrangement of parts MPEP § 2144.04 VI. C.), since the first SRAM cell of Liaw comprise the same core elements (i.e. first-fourth pass-gate transistors and shared second (120B of 101A/101C) and third (120B of 101B/101D) source/drain contacts) in a different arrangement, which if rearranged would result in a second source/drain contact over a source/drain region of the first pass-gate transistor in the first SRAM cell and a source/drain region of the second pass-gate transistor in the second SRAM cell; and a third source/drain contact over a source/drain region of the third pass-gate transistor in the first SRAM cell and a source/drain region of the fourth pass-gate transistor in the second SRAM cell.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Liaw (US 2022/0384456 A1, hereafter Liaw 456).
Re claim 9, Liaw discloses the method of claim 1.
But, fails to disclose wherein forming the first SRAM (101A/101B) comprises: forming an isolation transistor on a boundary of the first SRAM cell (101A/101B).
However,
Liaw 456 discloses in FIG. 13 wherein forming a first SRAM (Sy-1; [0023] and [0046]) comprises: forming an isolation transistor (240B; [0046]) on a boundary (interface of Sy-1/ Sy-2; [0023]) of the first SRAM cell (Sy-1).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Liaw, by forming forming an isolation transistor on a boundary of the first SRAM cell, as disclosed by Liaw 456, for electrical separation between adjacent cells (Liaw 456; [0023]).
Claims 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of CHANG et al (US 2020/0343185 A1, hereafter Chang) and LIN et al (US 2020/0020700 A1, hereafter Lin).
Re claim 12, Liaw discloses in FIGS. 1A-1C, 2A, 2B, 4A, 4C and 4E a method, comprising:
forming adjacent first (101A/101B; [0021]-[0022]) and second (101C/101D; [0021]-[0022]) static random access memory (SRAM) cells over a substrate (12; [0020]; [0025] and [0058]), wherein the first (101A/101B) and second (101C/101D) SRAM cells are arranged in a first direction (Y in FIG. 2A);
forming a first conductive line (left 120B in FIG. 2A; [0035]) electrically coupled to a source/drain region (114N; [0034]-[0035]) of a first pass-gate transistor (PG-1 of 101A; [0034]) in the first SRAM cell (101A/101B) and a source/drain region (114N; [0034]-[0035]) of a second pass-gate transistor (PG-1 of 101C; [0034]) in the second SRAM cell (101C/101D);
forming a second metal line (M1: BL; [0031] and [0033]) over the first conductive line (left 120B) and electrically coupled to the first metal line through a first interconnect via (126C; [0033] and [0036]).
Liaw fails to disclose forming a first metal line electrically coupled to the source/drain region (114N); forming the second metal line over the first metal line; and forming a third metal line over the second metal line and electrically coupled to the second metal line through a second interconnect via, wherein the third metal line comprises a first conductive pattern extending in a second direction different from the first direction and a second conductive pattern extends from a side of the first conductive pattern in the first direction, and both of the first and second conductive patterns of the third metal line partially overlap the second interconnect via.
However,
A. Chang discloses in FIG. 2 a method, comprising: forming a first metal line (240; [0027] and [0029]) electrically coupled to the source/drain region (of PG-1; [0027]); forming the second metal line (multi-layered 258; [0029] and [0034]) over the first metal line (240); and forming a third metal line (272; [0039]) over the second metal line (258) and electrically coupled (by contact) to the second metal line (258), wherein the third metal line (272) comprises a first conductive pattern (portion of 272 overlapping 240 overlapping 258) extending in a second direction (X: left-to-right) different from a first direction (Y: up-down) and a second conductive pattern (portion of 272 overlapping left side 240) extends from a side (left edge of 258) of the first conductive pattern (portion of 272 overlapping 240 overlapping 258) in the first direction (X).
And,
B. Lin discloses in FIG. 4 a method, comprising: forming a third metal line (M2; [0054]) over a second metal line (M1; [0054]) and electrically coupled to the second metal line (M1) through a second interconnect via (via1; [0054]), wherein the third metal line (M2) comprises a first conductive pattern (portion of M2 overlapping M1) extending in a second direction (X: left-to-right) different from a first direction (Y: up-down) and a second conductive pattern (portion of M2 beyond M1) extends from a side (at right edge of M1) of the first conductive pattern (portion of M2 overlapping M1) in the first direction (Y: up-down).
And,
C. With respect to the limitations of and both of the first and second conductive patterns of the third metal line partially overlap the second interconnect via, Liaw discloses an off-centered first interconnect via (126C; [0033] and [0036]), and Lin discloses off-set and/or off-centered vias (via0/via1/via2/via3; [0054]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Liaw, by using the first, second and third metal line formations of Chang with the second and third metal line formations of Lin, for forming a first metal line electrically coupled to the source/drain region; forming the second metal line over the first metal line; and forming a third metal line over the second metal line and electrically coupled to the second metal line through a second interconnect via, wherein the third metal line comprises a first conductive pattern extends in a second direction different from the first direction and a second conductive pattern extends from a side of the first conductive pattern in the first direction, and lastly, using the off-set and/or off-centered interconnect via disclosure of Liaw and Lin for the second interconnect via of Lin, such that both of the first and second conductive patterns of the third metal line partially overlap the second interconnect via, as an alternative method for forming vertical high-density (Lin; [0003] and [0009]), scaled down SRAM cells with reduce contact resistance (Chang; [0016]-[0017]).
Re claim 13, Liaw and Lin disclose the method of claim 12.
But, fails to disclose wherein the first and second interconnect vias are offset from each other in the first direction.
However, Liaw (126C) and Lin (via0/via1/via2/via3) both disclose off-set and/or off-centered vias, which through rearrangement of parts MPEP § 2144.04 VI. C.), would result in the first and second interconnect vias are offset from each other in the first direction, as part of the SRAM cells discussed for claim 12.
Re claim 14, Liaw and Chang and Lin disclose the method of claim 12.
But, fails to disclose wherein an area of the second interconnect via (Lin: via1) overlapped by the first (Chang: portion of 272 overlapping 240 overlapping 258) and second (Chang: portion of 272 overlapping left side 240) conductive patterns is greater than 75% of a total area of the second interconnect via (via1).
However, Liaw (126C) and Lin (via0/via1/via2/via3) both disclose off-set and/or off-centered vias, which through rearrangement of parts MPEP § 2144.04 VI. C.), can be configured wherein an area of the second interconnect via overlapped by the first and second conductive patterns is greater than 75% of a total area of the second interconnect via, as part of the SRAM cells discussed for claim 12.
Re claim 15, Liaw discloses the method of claim 12.
But, fails to disclose wherein the first and second conductive patterns of the third metal line are comprised in a bit line metal line.
However, the first (portion of 272 overlapping 240 overlapping 258) and second (portion of 272 overlapping left side 240) conductive patterns of the third metal line (272) of Chang is the uppermost metal layer, extends across multiple transistors consistent, and could be used as a bit line for the pass-gate transistors (PG-1) of the SRAM cells of Liaw, as part of the SRAM cells discussed for claim 12.
Re claim 16, Liaw discloses the method of claim 12.
But, fails to disclose wherein the second metal line comprises a word line metal line extending in the second direction and across the first and second SRAM cells.
However, Lin discloses second metal lines (M2; [0052]) comprising word line metal lines ([0052]), which through rearrangement of parts MPEP § 2144.04 VI. C.), can be configured as the word line metal line (M2: WL; [0033]) of Liaw extending in the second direction (X) and across the first (101A/101B) and second (101C/101D) SRAM cells, as part of the SRAM cells discussed for claim 12.
Re claim 17, Liaw discloses the method of claim 12, wherein forming the first and second SRAM further comprises: forming a plurality of semiconductor sheets over the substrate; and forming gate structures wrapping around the semiconductor sheets (see claim 6).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20230063098 A1 and US 20230063098 A1 disclose SRAM cell layouts with the claimed configurations of the pass-gate and pull-down transistors of claims 1; 12; and/or 18, which are directed to efficient low-cost methods of producing complex devices with increased density through smaller geometries.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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