DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/04/2024 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 1 of the instant application.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 2 of the instant application.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 5 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 3 of the instant application.
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 6 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 4 of the instant application.
Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 5 of the instant application.
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 4 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 6 of the instant application.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 2 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 8 of the instant application.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 3 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 9 of the instant application. Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 7 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 10 of the instant application. Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 11 of the instant application. Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 10 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 13 of the instant application.
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 12 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 14 of the instant application.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 13 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 13 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 15 of the instant application.
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 14 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 17 of the instant application.
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 14 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 18 of the instant application.
Claim 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 17 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 19 of the instant application.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of U.S. Patent No. 12,033,895. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 18 of U.S. Patent No. 12,033,895 recites all of the limitations in claim 20 of the instant application.
Prior art of record
Re claim 1, Kim et al. (2020/0411698) teaches a method of fabricating a semiconductor device (Figs. 11A-K), comprising: forming, over a substrate (101), alternating layers (Fig. 11D) of a first semiconductor layer (115) formed of a first semiconductor material ([33], “SiGe”) and a second semiconductor layer (141, 142, 143) formed of a second semiconductor material ([33], “Si”) different from the first semiconductor material ([33], “SiGe”), the first semiconductor layers (115) including a first sub-layer (“top layer”), a second sub-layer (“middle layer”) below the first sub-layer (“top layer”), and a third sub-layer (“bottom layer”) below the second sub-layer (“middle layer”); patterning the alternating layers of the first (115) and the second semiconductor layers (141, 142, 143) to form a stack of the alternating layers (Fig. 11F); and exposing, under etch conditions [83], lateral edges of the alternating layers to an etchant to selectively etch recesses in the lateral edges of the first, the second, and the third sub-layers [83]. Kim does not explicitly teach etch conditions, such that a first lateral depth of the first sub-layer is greater than a second lateral depth of the second sub-layer, and the second lateral depth of the second sub-layer is greater than a third lateral depth of the third sub-layer. Re claim 13, Kim et al. (2020/0411698) teaches a method of fabricating a semiconductor device (Figs. 11A-K), comprising: providing a substrate (101); forming alternating layers (Fig. 11D) of first semiconductor layers (115) and second semiconductor layers (141, 142, 143), the first semiconductor layers (115) formed of a first semiconductor material ([33], “SiGe”), the second semiconductor layers (141, 142, 143) formed of a second semiconductor material ([33], “Si”), the first semiconductor layers (115) including a first semiconductor sub-layer (“top layer”), a second semiconductor sub-layer (“middle layer”) below the first semiconductor sub-layer (“top layer”), and a third semiconductor sub-layer (“bottom layer”) below the second semiconductor sub-layer (“middle layer”); patterning the alternating layers of the first semiconductor layers (115) and the second semiconductor layers (141, 142, 143) to form a stack of the alternating layers (Fig. 11F) and to expose lateral edges of the alternating layers (Fig. 11F); and exposing, under etch conditions [83], the lateral edges of the alternating layers to an etchant to selectively etch recesses in the lateral edges of the first, the second, and the third semiconductor sub-layers [83].
Kim does not explicitly teach etch conditions, such that a first lateral depth of the first semiconductor sub-layer is less than a second lateral depth of the second semiconductor sub-layer, and the second lateral depth of the second semiconductor sub-layer is less than a third lateral depth of the third semiconductor sub-layer.
Re claim 17, Kim et al. (2020/0411698) teaches a method of fabricating a semiconductor device (Figs. 11A-K), comprising: forming alternating layers (Fig. 11D) of first semiconductor layers (115) of a first semiconductor material ([33], “SiGe”) and second semiconductor layers (141, 142, 143) of a second semiconductor material ([33], “Si”) different from the first semiconductor material ([33], “SiGe”) over a substrate (101), such that a stack of the alternating layers is formed (Fig. 11D), the first semiconductor layers (115) including at least a first sub-layer (“top layer”), a second sub-layer (“middle layer”) below the first sub-layer (“top layer”), and a third sub-layer (“bottom layer”) below the second sub-layer (“middle layer”); and exposing, under etch conditions [83], lateral edges of the alternating layers of the stack to an etchant to selectively etch recesses in the lateral edges of the first sub-layer, and the second sub-layer, and the third sub-layer of the first semiconductor layers [83].
Kim does not explicitly teach etch conditions, such that a first lateral depth of the first sub-layer is greater than a second lateral depth of the second sub-layer, and the second lateral depth of the second sub-layer is greater than a third lateral depth of the third sub-layer.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not anticipate or make obvious the method of claim 1, including each of the limitations and specifically etch conditions, such that a first lateral depth of the first sub-layer is greater than a second lateral depth of the second sub-layer, and the second lateral depth of the second sub-layer is greater than a third lateral depth of the third sub-layer, for the same reasons as mentioned for claim 1 in the prior art of record above. The prior art of record does not anticipate or make obvious the method of claim 13, including each of the limitations and specifically etch conditions, such that a first lateral depth of the first semiconductor sub-layer is less than a second lateral depth of the second semiconductor sub-layer, and the second lateral depth of the second semiconductor sub-layer is less than a third lateral depth of the third semiconductor sub-layer, for the same reasons as mentioned for claim 13 in the prior art of record above.
The prior art of record does not anticipate or make obvious the method of claim 17, including each of the limitations and specifically such that a first lateral depth of the first sub-layer is greater than a second lateral depth of the second sub-layer, and the second lateral depth of the second sub-layer is greater than a third lateral depth of the third sub-layer, for the same reasons as mentioned for claim 17 in the prior art of record above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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