DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on May 14, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6, 9-14, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2013/0307140 A1 to Huang et al. (“Huang”) in view of U.S. Patent Application Publication No. 2018/0247916 A1 to Lee et al. (“Lee”). As to claim 1, Huang in view of Lee discloses a package structure, comprising: a first packaging layer (558); a first chip (450) attached to a first surface of the first packaging layer (558); a second packaging layer (532a) disposed over the first chip (450) and the first packaging layer (558); a rewiring layer (534, 532b/180) extending on an upper surface of the second packaging layer (532a), electrically connected to the first chip (450); a through via (460 in 532a) conformally covering an opening (filled) extending from the upper surface to a lower surface of the second packaging layer (532a), thereby connecting the rewiring layer (534, 532b/180) at the upper surface of the second packaging layer (532a), wherein the through via (460 in 532a) has a recessed upper surface directly over the opening (filled), and the through via (460 in 532a) is within a perimeter of the first chip (450); a second chip (191) disposed on the rewiring layer (534, 532b/180), electrically connected to the rewiring layer (534, 532b/180); a plurality of conductive posts (415) extending from the lower surface of the second packaging layer (532a) to the first surface of the first packaging layer (558); and a plurality of conductive terminals (560, 544, 430 in contact with 415) connecting the plurality of conductive posts (415) at the first surface of the first packaging layer (558), wherein an orthographic projection of the plurality of conductive terminals (560, 544, 430 in contact with 415) onto the first surface of the first packaging layer (558) is outside of the perimeter of the first chip (450) (See Huang Fig. 2, Fig. 4, Fig. 5, ¶ 0022, ¶ 0027, ¶ 0033, ¶ 0034, ¶ 0035, ¶ 0036 and Lee Fig. 2, ¶ 0083-¶ 0112) (Notes: the plurality of conductive terminals are met by the specific connection to the conductive posts that are outside of the first chip and the packaging layer is interpreted as a layer integrated within the package structure), where the second chip of additional passive and active components integrated with the first chip provides more functionalities. As to claim 2, Huang further discloses wherein the opening (filled) has a first width at the upper surface greater than a second width at the lower surface of the second packaging layer (532a) (See Fig. 5). As to claim 3, Huang further discloses wherein the through via (460 in 532a) is in direct contact with a connector (528) over the first chip (450) at the lower surface of the second packaging layer (532a), so that the rewiring layer (534, 532b) and the through via (460 in 532a) are electrically connected to the first chip (450) by the connector (528) over the first chip (450) (See Fig. 5, ¶ 0034). As to claim 4, Huang in view of Lee further discloses wherein one or more solder balls (465/190) are formed on the rewiring layer (534, 532b/180), and the one or more solder balls (465/190) and the second chip (191) are arranged horizontally on the same plane (See Lee Fig. 2, ¶ 0112). As to claim 5, Huang in view of Lee discloses further comprising: an encapsulant (410/140, 170) disposed on the first packaging layer (558) to laterally encapsulate the first chip (450), wherein the plurality of conductive posts (415/120, 150) are embedded in the encapsulant (410/140, 170) to laterally surround the first chip (450), wherein the encapsulant (410/140, 170) is in direct contact with sidewalls of the plurality of conductive posts (415/120, 150); and a package substrate (external elements) bonded to a second surface of the first packaging layer (588) opposite to the first surface through the plurality of conductive terminals (560, 544, 430 in contact with 415), wherein a region between the first surface and the second surface of the first packaging layer (558) directly under the first chip (450) is substantially free of the plurality of conductive terminals (560, 544, 430 in contact with 415) (See Huang Fig. 2, Fig. 5, ¶ 0022, ¶ 0027, ¶ 0033, ¶ 0036 and Lee Fig. 2) (Notes: the solder balls are to be further connect to additional external elements such as a package substrate, that is also taught by cited Marimuthu. Further, any particular region under the first chip without any element but only the material of the first packaging layer is free of the plurality of conductive terminals). As to claim 6, Huang further discloses wherein the plurality of conductive terminals (560, 544, 430 in contact with 415) is in direct contact with the plurality of conductive posts (415) respectively (See Fig. 2, Fig. 4, Fig. 5). As to claim 9, Huang in view of Lee discloses a method of forming a package structure, comprising: forming a first packaging layer (558); forming a first chip (450) to attached to a first surface of the first packaging layer (558); forming a second packaging layer (532a) over the first chip (450) and the first packaging layer (558); forming a rewiring layer (534, 532b/180) to extend on an upper surface of the second packaging layer (532a), to be electrically connected to the first chip (450); forming a through via (460 in 532a) conformally cover an opening (filled) extending from the upper surface to a lower surface of the second packaging layer (532a), thereby connecting the rewiring layer (534, 532b/180) at the upper surface of the second packaging layer (532a), wherein the through via (460 in 532a) has a recessed upper surface directly over the opening (filled), and the through via (460 in 532a) is within a perimeter of the first chip (450); forming a second chip (191) on the rewiring layer (534, 532b/180), to be electrically connected to the rewiring layer (534, 532b/180); forming a plurality of conductive posts (415) extending from the lower surface of the second packaging layer (532a) to the first surface of the first packaging layer (558); and forming a plurality of conductive terminals (560, 544, 430 in contact with 415) connecting the plurality of conductive posts (415) at the first surface of the first packaging layer (558), wherein an orthographic projection of the plurality of conductive terminals (560, 544, 430 in contact with 415) onto the first surface of the first packaging layer (558) is outside of the perimeter of the first chip (450) (See Huang Fig. 2, Fig. 4, Fig. 5, ¶ 0022, ¶ 0027, ¶ 0033, ¶ 0034, ¶ 0035, ¶ 0036 and Lee Fig. 2, ¶ 0083-¶ 0112) (Notes: the plurality of conductive terminals are met by the specific connection to the conductive posts that are outside of the first chip and the packaging layer is interpreted as a layer integrated within the package structure), where the second chip of additional passive and active components integrated with the first chip provides more functionalities. As to claim 10, Huang further discloses wherein the opening (filled) has a first width at the upper surface greater than a second width at the lower surface of the second packaging layer (532a) (See Fig. 5). As to claim 11, Huang further discloses wherein the through via (460 in 532a) is in direct contact with a connector (528) over the first chip (450) at the lower surface of the second packaging layer (532a), so that the rewiring layer (534, 532b) and the through via (460 in 532a) are electrically connected to the first chip (450) by the connector (528) over the first chip (450) (See Fig. 5, ¶ 0034). As to claim 12, Huang in view of Lee further discloses wherein one or more solder balls (465/190) are formed on the rewiring layer (534, 532b/180) (See Huang Fig. 5, ¶ 0035 and Lee Fig. 2) As to claim 13, Huang in view of Lee discloses further comprising: forming an encapsulant (410/140, 170) on the first packaging layer (558) to laterally encapsulate the first chip (450), wherein the plurality of conductive posts (415/120, 150) are embedded in the encapsulant (410/140, 170) to laterally surround the first chip (450); and bonding a package substrate (external elements) to a second surface of the first packaging layer (558) opposite to the first surface through the plurality of conductive terminals (560, 544, 430 in contact with 415), wherein a region between the first surface and the second surface of the first packaging layer (558) directly under the first chip (450) is substantially free of the plurality of conductive terminals (560, 544, 430 in contact with 415) (See Huang Fig. 2, Fig. 5, ¶ 0022, ¶ 0027, ¶ 0033, ¶ 0036 and Lee Fig. 2) (Notes: the solder balls are to be further connect to additional external elements such as a package substrate, that is also taught by cited Marimuthu. Further, any particular region under the first chip without any element but only the material of the first packaging layer is free of the plurality of conductive terminals) (See Huang Fig. 2, Fig. 5, ¶ 0022, ¶ 0027, ¶ 0033, ¶ 0036 and Lee Fig. 2). As to claim 14, Huang further discloses wherein the plurality of conductive terminals (560, 544, 430 in contact with 415) is in direct contact with the plurality of conductive posts (415) respectively (See Fig. 2, Fig. 4, Fig. 5). As to claim 21, Huang further discloses wherein the first packaging layer (558) further extends below the encapsulant (410) and the plurality of conductive posts (415) (See Fig. 5). As to claim 22, Huang in view of Lee further discloses wherein the plurality of conductive terminals (560, 544, 430 in contact with 415) is partially embedded in the first packaging layer (558) (See Fig. 5).
Claim(s) 15-19 and 23 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2013/0037950 A1 to Yu et al. (“Yu”) in view of U.S. Patent Application Publication No. 2018/0247916 A1 to Lee et al. (“Lee”) and U.S. Patent No. 6,541,872 B1 to Schrock et al. (“Schrock”). As to claim 15, Yu in view of Lee and Schrock discloses a package structure, comprising: a first packaging layer (108); a die stack structure (Chip 2, Chip 3) attached to a first surface of the first packaging layer (108), wherein the die stack structure (Chip 2, Chip 3) comprises: a first die (Chip 2) and a second die (Chip 3) bonded together through a bonding structure (124/160a/40), and the bonding structure (124/160a/40) comprising: a blocking layer (50) between a first bonding dielectric material (46) and a second bonding dielectric material (48), wherein a material of the blocking layer (50) is different from the first (46) and second (48) bonding dielectric materials, wherein the first die (Chip 2) is electrically connected to the second die (Chip 3) through the bonding structure (124/160a/40); a second packaging layer (UBM under 112) disposed over the die stack structure (Chip 2, Chip3) and the first packaging layer (108); a rewiring layer (110, 112 top/180) extending on an upper surface of the second packaging layer (UBM under 112), electrically connected to the die stack structure (Chip 2, Chip 3); a through via (112 in opening) conformally covering an opening (filled) extending from the upper surface to a lower surface of the second packaging layer (UBM under 112), thereby connecting the rewiring layer (110, 112 top/180) at the upper surface of the second packaging layer (UBM under 112), wherein the through via (112 in opening) has a recessed upper surface directly over the opening (filled); an encapsulant (106) continuously extending from the lower surface of the second packaging layer (UBM under 112) to the first surface of the first packaging layer (108) to laterally encapsulate the die stack structure (Chip 2, Chip 3); and a chip (191) disposed on the rewiring layer (110, 112 top/180), electrically connected to the rewiring layer (110, 112 top/180) (See Yu Fig. 1, ¶ 0013-¶ 0020, Lee Fig. 2, ¶ 0077, ¶ 0083-¶ 0112, and Schrock Fig. 4, Column 6, lines 3-46), where the bonding structure of single and multi-layered tapes are well-known to provide the bonding between the first and second dies and can be a dielectric material to inhibit electrical conductivity, a thermally conductive material, and an electrically conductive material to provide direct electrical connection between the first die and the second die to obtain a higher integration, and the chip of additional passive and active components integrated with the die stack structure provides more functionalities (Notes: the packaging layer is interpreted as a layer integrated within the package structure/base and the blocking layer serves as a physical barrier). As to claim 16, Yu in view of Lee discloses further comprising one or more solder balls (110/190) on the rewiring layer (112 top/180), wherein the one or more solder balls (110/190) and the chip (191) are arranged horizontally on the same plane (See Lee Fig. 2). As to claim 17, Yu further discloses wherein the die stack structure (Chip 2, Chip 3) further comprises: an insulating encapsulation (106 between 102 on second die) on the second die (Chip 3) to laterally encapsulate the first die (Chip 2), wherein the encapsulant (106) further laterally encapsulates the insulating encapsulation (106 between 102 on second die); a redistribution circuit structure (to 122) on a back side of the first die (Chip 2) and on the insulating encapsulation (106 between 102 on second die); at least one through dielectric via (102) penetrating through the insulating encapsulation (106 between 102 on second die) to electrically connect the second die (Chip 3) and the redistribution circuit structure (to 122); and a plurality of contacts (122) disposed on the redistribution circuit structure (to 122), wherein the rewiring layer (110, 112 top/180) is in contact with the plurality of contacts (122) by the through via (102) (See Fig. 1). As to claim 18, Yu discloses further comprising: a plurality of conductive posts (102) embedded in the encapsulant (106) to laterally surround the die stack structure (Chip 2, Chip 3), wherein the plurality of conductive posts (102) continuously extend from the lower surface of the second packaging layer (UBM under 112) to the first surface of the first packaging layer (108); and a package substrate (120) bonded to a second surface of the first packaging layer (108) opposite to the first surface through a plurality of conductive terminals (104) (See Fig. 1). As to claim 19, Yu further discloses wherein the plurality of conductive terminals (104) is in direct contact with the plurality of conductive posts (102) respectively (See Fig. 1). As to claim 23, Yu further discloses wherein the through via (112 in opening) is directly over the die stack structure (Chip 2, Chip 3) to connect the rewiring layer (110, 112 top) and the die stack structure (Chip 2, Chip 3) (See Fig. 1).
Response to Arguments
Applicant's arguments with respect to claims 1, 9, and 15 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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