Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's amendment/arguments filed on 12/23/25 as being acknowledged and entered. By this amendment claims 1-20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8, 10-11 and 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zang et al. (US PGPub 2019/0043758).
Claim 1: Zang teaches (Fig. 1, 10-11) static random access memory (SRAM) cell, comprising: a first pull-up (PU) transistor comprising a first gate structure; a second PU transistor [0003-0004] comprising a second gate structure, wherein the second gate structure comprises a gate stack and gate spacers (Fig. 10); and a first butted contact (126), wherein the first butted contact electrically connects a first terminal (112A) of the first PU transistor to the second gate structure (106), wherein the first butted contact directly contacts each of a top surface and a sidewall of the gate stack, and a first gate spacer of the gate spacers (110B) is between a portion of the first butted contact and the gate stack, and a second gate spacer of the gate spacer extends above a top surface of the first gate spacer (Fig. 10). As seen in the figure below the first interface between butted contact (126) and the gate stack (top surface) is aligned with the second interface (contact at 110r) between the first gate spacer (110b) and the gate stack. The current claim language does not describe how the interfaces align, for example are they horizontally or vertically aligned, aligned on the same plane, etc. Applicant’s figure 7B does not appear to show that these interfaces are aligned in a particular way, only that the first interface between the butted contact and the gate stack is the same sidewall of the gate stack as the second interface between the first gate spacer and the gate stack. This relationship is not specified by the current claim language.
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Claim 2: Zang teaches (Fig. 1, 10-11) the first terminal is a shared terminal with the second PU transistor.
Claim 3: Zang teaches (Fig. 1, 10-11) the first terminal is between the first gate structure and the second gate structure.
Claim 4: Zang teaches (Fig. 1, 10-11) a second butted contact, wherein the second butted contact electrically connects a second terminal of the second PU transistor to the first gate structure.
Claim 5: Zang teaches (Fig. 1, 10-11) the second terminal is separated from the first terminal.
Claim 6: Zang teaches (Fig. 1, 10-11) the first butted contact extends in a first direction parallel to a substrate, the first gate structure extends in a second direction parallel to the substrate, and the first direction is perpendicular to the second direction.
Claim 8: Zang teaches (Fig. 1, 10-11) the gate spacers are between a portion of the gate stack and the first butted contact.
Claim 10: Zang teaches (Fig. 1, 10-11) comprising a second contact electrically connected to a second terminal of the first PU transistor, wherein the first gate structure is between the first butted contact and the second contact.
Claim 11: Zang teaches (Fig. 1, 10-11) (see claim 1) semiconductor device, comprising: a first gate structure extending across a first active region; a second gate structure, wherein the second gate structure comprises a gate stack and gate spacers, wherein a thickness of the gate stack is substantially uniform, and the gate stack partially overlaps the first active region; and a first butted contact, wherein the first butted contact electrically connects a first source/drain (S/D) region to the second gate structure, the first butted contact interfacing with each of a top surface and a sidewall of a gate electrode of the gate stack, and the first S/D region is between the first gate structure and the second gate structure. The claim does not specify in which direction the thickness is. Zhang’s gate stack has uniform thickness in the plan view of Figures 9.
Claim 16: Zang teaches (Fig. 1, 10-11) a second butted contact, wherein the second butted contact electrically connects a second S/D region in the second active region to the first gate structure.
Claim 17: Zang teaches (Fig. 1, 10-11) comprising an isolation structure between the first active region and the second active region.
Claim 18: Zang teaches (Fig. 1, 10-11) method of making a static random access memory (SRAM) cell, comprising: forming a first gate structure; forming a second gate structure, wherein the second gate structure comprises a gate stack and gate spacers (Fig. 2); depositing a dielectric layer (120) over the first gate structure and the second gate structure (Fig. 3); etching the dielectric layer to define an opening exposing a first source/drain (S/D) region between the first gate structure and the second gate structure, wherein the opening further exposes a top surface and a sidewall of the gate stack (Fig. 4), and etching the dielectric layer comprises partially removing the gate spacers to expose the sidewall of the gate stack (Fig. 5-6); maintaining a location of the sidewall of the gate stack during the etching of the dielectric layer (Fig 6-7); and depositing a conductive material into the opening, wherein the conductive material electrically connects the first S/D region to the gate stack (Fig. 10). Zhang teaches maintain the location of the sidewall 106x while etching the dielectric layer between figures 6-7. The claim language does not specify that the gate sidewall that is maintained is in contact with the partially removed gate spacer.
Claim 19: Zang teaches (Fig. 1, 10-11) forming a first pull up (PU) transistor comprising the first gate structure; and forming a second PU transistor comprising the second gate structure.
Claim 20: Zang teaches (Fig. 1, 10-11) partially removing the gate spacers shortening a first gate spacer of the gate spacers; and maintaining a second gate spacer of the gate spacers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US PGPub 2019/0043758)
Claim 12: Zang teaches an isolation structure (20) in a substrate, wherein the isolation structure contacts the first active region. Isolation regions between active regions are well known in the art.
Claims 7, 9, and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zang et al. (US PGPub 2019/0043758), as applied to claim 1, 6, and 11, in view of Chang et al. (US PGPub 2008/0303105).
Regarding claim 7, as described above, Zang substantially reads on the invention as claimed, except Zang does not teach the second gate structure extends beyond the first gate structure in the second direction. Chang teaches (Fig. 13A-C) the second gate structure extends beyond the first gate structure in the second direction to reduce on current pull-up without significantly effecting other transistor parameters [0011]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Zang to have had the second gate structure extends beyond the first gate structure in the second direction to reduce on current pull-up without significantly effecting other transistor parameters as taught by Chang [0011].
Claim 9: Chang teaches (Fig. 13A-C) the first butted contact has a tapered profile.
Claim 13: Chang teaches (Fig. 13A-C) the second gate structure partially overlaps the isolation structure.
Claim 14: Chang teaches (Fig. 13A-C) a second active region, wherein the first gate structure extends across the second active region, and the second gate structure is offset from the second active region in a direction parallel to a top surface of the second active region.
Claim 15: Chang teaches (Fig. 13A-C) a second active region, wherein the second gate structure extends across the second active region, and the first gate structure partially overlaps the second active region.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814