Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/4/26 has been entered.
Applicant's amendment/arguments filed on 6/4/26 as being acknowledged and entered. By this amendment claims 1-20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18 and 20 are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Oosuka et al. (US PGPub 2009/0108379).
Claim 18: Oosuka teaches a method of making a static random access memory (SRAM) cell, comprising: forming a first gate structure; forming a second gate structure, wherein the second gate structure comprises a gate stack and gate spacers (Fig. 2A); depositing a dielectric layer (81) [0045] over the first gate structure and the second gate structures wherein the dielectric layer is between the first gate structure and the second gate structure, and a top surface of the dielectric layer is above a topmost surface of the gate stack (Fig. 2B); etching the dielectric layer to define an opening exposing a first source/drain (S/D) region between the first gate structure and the second gate structure, wherein the opening further exposes a top surface and a sidewall of the gate stack, and etching the dielectric layer comprises partially removing the gate spacers to expose the sidewall of the gate stack (Fig. 2C, 3A); maintaining a location of the sidewall of the gate stack during the etching the dielectric layer; and depositing a conductive material into the opening, wherein the conductive material electrically connects the first S/D region to the gate stack (Fig. 3B).
Claim 20: Oosuka teaches (Fig. 2A-3C) partially removing the gate spacers shortening a first gate spacer of the gate spacers; and maintaining a second gate spacer of the gate spacers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw et al. (US Patent 8,315,084)
Claim 19: Zang teaches (Fig. 1, 10-11) forming a first pull up (PU) transistor comprising the first gate structure; and forming a second PU transistor comprising the second gate structure. It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior arts teach the identical chemical structure the properties applicant discloses and/or claims are necessarily present. In re Spada, 15 USPQ 2d 1655, 1658 (Fed. Cir. 1990). The use of the transistors as pull up transistors does not add physical attributes or method steps to the claim. The prior art reads on the physical attributes and method steps claimed and therefore would be applicable to pull up transistors.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw et al. (US Patent 8,315,084) in view of Oosuka et al. (US PGPub 2009/0108379).
Claim 1: Liaw teaches (Fig. 4) static random access memory (SRAM) cell, comprising: a first pull-up (PU-1) transistor comprising a first gate structure (136); a second PU transistor (PU-2) comprising a second gate structure (138) offset from the first PU transistor in a first direction, wherein the second gate structure comprises a gate stack, and the gate stack has a substantially uniform width in the first direction; and a first butted contact, wherein the first butted contact electrically connects a first terminal of the first PU transistor to the second gate structure. Liaw does not teach gate spacers, and wherein the first butted contact is on a top surface and a first sidewall of the gate stack, a first gate spacer of the gate spacers is between a portion of the first butted contact and the gate stack, a first interface between the first butted contact and the gate stack is aligned with a second interface between the first gate spacer and the gate stack, and a second gate spacer of the gate spacers extends above a top surface of the first gate spacer. Oosuka teaches (Fig. 9) teach gate spacers, and wherein the first butted contact (60) is on a top surface and a first sidewall of the gate stack, a first gate spacer of the gate spacers is between a portion of the first butted contact and the gate stack, a first interface between the first butted contact and the gate stack is aligned with a second interface between the first gate spacer and the gate stack, and a second gate spacer of the gate spacers extends above a top surface of the first gate spacer to reduce wiring resistance [0005]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the butted contact and spacer structure claimed taught by Liaw as claimed to reduce wiring resistance as taught by Oosuka [0005].
Claim 2: Liaw teaches (Fig. 4) the first terminal is a shared terminal with the second PU transistor.
Claim 3: Liaw teaches (Fig. 4) the first terminal is between the first gate structure and the second gate structure.
Claim 4: Liaw teaches (Fig. 4) a second butted contact, wherein the second butted contact electrically connects a second terminal of the second PU transistor to the first gate structure.
Claim 5: Liaw teaches (Fig. 4) the second terminal is separated from the first terminal.
Claim 6: Liaw/Oosuka teaches (Fig. 4/9) the first butted contact extends in a first direction parallel to a substrate, the first gate structure extends in a second direction parallel to the substrate, and the first direction is perpendicular to the second direction.
Claim 7: Liaw teaches (Fig. 4) the second gate structure extends beyond the first gate structure in the second direction
Claim 8: Oosuka teaches (Fig. 9) the gate spacers are between a portion of the gate stack and the first butted contact.
Claim 9: Oosuka teaches (Fig. 9) the first butted contact has a tapered profile.
Claim 10: Liaw/Oosuka teaches (Fig. 4/9) a second contact electrically connected to a second terminal of the first PU transistor, wherein the first gate structure is between the first butted contact and the second contact.
Claim 11: Liaw teaches (Fig. 4) a semiconductor device, comprising: a first gate structure extending across a first active region; a second gate structure, wherein the second gate structure comprises a gate stack, wherein a thickness of the gate stack is substantially uniform, the thickness being a height of the gate stack perpendicular to a top surface of the first active region, and a top surface of the gate stack is planar, and the gate stack partially overlaps the first active region; and a first butted contact, wherein the first butted contact electrically connects a first source/drain (S/D) region to the second gate structure, and the first S/D region is between the first gate structure and the second gate structure. Liaw does not teach gate spacers or the first butted contact interfacing with each of a top surface and a sidewall of a gate electrode of the gate stack. Oosuka teaches (Fig. 9) teach gate spacers and the first butted contact interfacing with each of a top surface and a sidewall of a gate electrode of the gate stack to reduce wiring resistance [0005]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the butted contact and spacer structure claimed taught by Liaw as claimed to reduce wiring resistance as taught by Oosuka [0005].
Claim 12: Liaw/Oosuka teaches (Fig. 4/9) teaches an isolation structure in a substrate, wherein the isolation structure contacts the first active region. Isolation regions between active regions are well known in the art.
Claim 13: Oosuka teaches (Fig. 9) the second gate structure partially overlaps the isolation structure.
Claim 14: Liaw/Oosuka teaches (Fig. 4/9) a second active region, wherein the first gate structure extends across the second active region, and the second gate structure is offset from the second active region in a direction parallel to a top surface of the second active region.
Claim 15: Liaw/Oosuka teaches (Fig. 4/9) a second active region, wherein the second gate structure extends across the second active region, and the first gate structure partially overlaps the second active region.
Claim 16: Liaw teaches (Fig. 4) a second butted contact, wherein the second butted contact electrically connects a second S/D region in the second active region to the first gate structure.
Claim 17: Liaw/Oosuka teaches (Fig. 4/9) comprising an isolation structure between the first active region and the second active region.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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