DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Information Disclosure Statement
Examiner notes that the foreign patent documents cited in the IDS filed 6/5/2024 can be found in the IFW of the parent cases.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 4, 6, 7, 11, 12, 14, 15, 17, and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 5, and 7 of U.S. Patent No. 11,621,338 (hereinafter US Patent). Although the claims at issue are not identical, they are not patentably distinct from each other because:
As to claim 1: Claim 1 of US Patent discloses all limitations of instant claim 1 where the first conductive layer is the second metal gate layer and the second conductive layer is the first metal gate layer.
As to claim 2: Claim 1 of US Patent discloses all limitations of instant claim 2 where the first conductive layer is the second metal gate layer and the second conductive layer is the first metal gate layer.
As to claim 4: Claim 7 of US Patent discloses all limitations of instant claim 4.
As to claim 6: Claim 4 of US Patent discloses all limitations of instant claim 6 where the semiconductor layer is the second silicon-based capping layer of claim 2 that can comprise SiC, which is a semiconductor material, in claim 4.
As to claim 7: Claim 2 of US Patent discloses all limitations of instant claim 7 where the semiconductor layer is the second silicon-based capping layer.
As to claim 11: Claim 4 of US Patent discloses all limitations of instant claim 11 where the metal-based layer is the first metal gate layer of claim 1 and the oxygen barrier layer is the silicon nitride layer of claim 4 as silicon nitride is inherently able to block oxygen.
As to claim 12: Claim 4 of US Patent discloses all limitations of instant claim 12 where the oxygen barrier layer is the silicon nitride layer of claim 4 as silicon nitride is a silicon-based layer.
As to claim 14: Claim 5 of US Patent discloses all limitations of instant claim 14 as a dielectric having a dielectric constant higher than about 3.9 is a high-k dielectric.
As to claim 15: Claim 7 of US Patent discloses all limitations of instant claim 15.
As to claim 17: Claim 4 of US Patent discloses all limitations of instant claim 17 where the metal layer is the first metal gate layer of claim 1 and the semiconductor layer is the second silicon-based capping layer of claim 2 that can comprise SiC, which is a semiconductor material, in claim 4.
As to claim 18: Claim 4 of US Patent discloses all limitations of instant claim 18 where the semiconductor layer is the silicon carbide layer of claim 4 as silicon carbide is a semiconductor material.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, and 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sharma et al (US 2023/0223475 and Sharma hereinafter).
As to claims 1, 2, 4, and 5: Sharma discloses [claim 1] a semiconductor device (Figs. 8A and 8B; 120; [0041]), comprising: a substrate (140; [0041]); a fin structure (102/132; [0041]) disposed on the substrate (140); and a gate structure (100; [0041]), comprising: a first conductive layer (104 can be titanium; [0029]) disposed on the fin structure (102/132); a ferroelectric layer (105; [0025]) disposed on the first conductive layer (104); and a second conductive layer (108; [0022]) disposed on the ferroelectric layer (105); [claim 2] wherein each of the first (104) and second (108) conductive layers comprises a metal layer (104 can be titanium and 108 can be titanium, aluminum, palladium, etc.; [0022] and [0029]); [claim 4] wherein the ferroelectric layer (105) comprises a crystalline structure (at least some of the ferroelectric layer 105 has a crystalline (orthorhombic) structure; [0027]); [claim 5] wherein the second conductive layer (108) is in contact with (108 can be in direct contact with 105 as intervening layer 106 is optional and can be omitted; [0023], [0030], and [0042]) the ferroelectric layer (105).
Claims 11-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Song et al (US 2020/0365733 and Song hereinafter).
As to claims 11-16: Song discloses [claim 11] a semiconductor device (Fig. 2; [0027]), comprising: a substrate (10; [0029]); and a gate structure (GS1; [0029]), comprising: a ferroelectric layer (35; [0032]) disposed on the substrate (10); a metal-based layer (37 can be TiN or TaN; [0032] and [0034]) disposed on the ferroelectric layer (35); and an oxygen barrier layer (42 can be SiN, which is an oxygen barrier material; [0034]) disposed on the metal-based layer (37); [claim 12] wherein the oxygen barrier layer (42) comprises a silicon-based layer (42 can be SiN, which is an oxygen barrier material, and is silicon-based; [0034]); [claim 13] wherein the metal-based layer (37) comprises a metal nitride layer (37 can be TiN or TaN; [0034]); [claim 14] wherein the ferroelectric layer (35) comprises a high-k dielectric layer (35 can be HfO2, which is a high-k dielectric; [0034]); [claim 15] wherein the ferroelectric layer (35 can be in a crystalline phase) comprises a crystalline structure ([0044]); [claim 16] further comprising an oxide layer (31 can be silicon oxide; [0033]) disposed between the substrate (10) and the ferroelectric layer (35).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Hu (US 2017/0162702 and Hu hereinafter).
Sharma discloses wherein the second conductive layer (Figs. 8A and 8B; 108) comprise a metal nitride layer (108 can be titanium nitride, tantalum nitride, or tungsten nitride; [0022]).
Sharma fails to expressly disclose wherein the first conductive layer comprise a metal nitride layer.
Sharma discloses in [0029] that the first conductive layer 104 can comprise a metal like titanium.
Hu discloses in Fig. 4B and [0038] a ferroelectric finfet with two metal layers (410 and 404) sandwiching a ferroelectric layer 104 where the first conductive layer of Sharma and as claimed is analogous to the internal gate 410. Hu discloses that the internal gate (first conductive layer) can comprise TiN or TaN, see [0042].
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing a material from the list of Hu to be the material for the first conductive layer of Sharma, specifically TiN or TaN, instead of Ti; if this leads to the anticipated success, in the instant case a layer that can act as a conductive layer to operate the transistor, it is likely the product not of innovation but of ordinary skill.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Cheng et al (US 2020/0388694 and Cheng hereinafter).
As to claims 8 and 9: Although the structure disclosed by Sharma shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose:
[claim 8] further comprising a semiconductor layer disposed on and in contact with the second conductive layer; [claim 9] further comprising an oxygen barrier layer disposed on and in contact with the second conductive layer.
Cheng discloses in Fig. 15 a transistor structure comprising a layer 138 over and in contact with the gate electrode 136, see [0048]. The layer 138 can comprise silicon carbide, which is a wide bandgap semiconductor layer, or silicon nitride, which is an oxygen barrier material, see [0052].
Given the teachings of Cheng, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Sharma by employing the well-known or conventional features of gate cap formation, such as displayed by Cheng, by employing a gate capping structure comprising either a semiconductor layer (such as silicon carbide) or an oxygen barrier layer (such as silicon nitride) to place in contact with the second conductive layer of Sharma in order to protect the gate structure during further processing ([0052]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Song.
Although the structure disclosed by Sharma shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose:
further comprising an oxide layer disposed between the fin structure and the first conductive layer.
Song discloses in Fig. 2 and [0032]-[0033] a ferroelectric finfet with an oxide layer 31 in direct contact with the fin.
A person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to form an oxide layer as in Song in direct contact with the fin 102/132 of Sharma (such that the oxide layer 31 would be between the fin 102/132 and the first conductive layer 104) in order to provide a transistor structure with a lattice matched dielectric in contact with the channel region and to electrically insulate the gate conductive layers from the channel layer ([0033]).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Cheng.
As to claims 17-20: Sharma discloses [claim 17] a semiconductor device (Figs. 8A and 8B; 120; [0041]), comprising: a substrate (140; [0041]); a fin structure (102/132; [0041]) disposed on the substrate (140); a ferroelectric layer (105; [0025]) disposed on the fin structure (102/132); a metal layer (108; [0022]) disposed on the ferroelectric layer (105); [claim 19] wherein the ferroelectric layer (105) comprises a hafnium-based oxide layer (105 can be hafnium silicon oxide, hafnium zirconium oxide, etc.; [0025]); [claim 20] wherein the metal layer (108) comprises titanium, tantalum, titanium-aluminum, tungsten, or cobalt (108 can be titanium, tantalum, titanium-aluminum, tungsten nitride, or cobalt; [0022]).
Sharma fails to expressly disclose [claim 17] a semiconductor layer disposed on the metal layer; [claim 18] wherein the semiconductor layer comprises a silicon-based layer.
Cheng discloses in Fig. 15 a transistor structure comprising a layer 138 over and in contact with the gate electrode 136, see [0048]. The layer 138 can comprise silicon carbide, which is a silicon-based wide bandgap semiconductor layer.
Given the teachings of Cheng, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Sharma by employing the well-known or conventional features of gate cap formation, such as displayed by Cheng, by employing a gate capping structure comprising a semiconductor layer (such as silicon carbide) to place in contact with the second conductive layer of Sharma in order to protect the gate structure during further processing ([0052]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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