DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/05/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12/033,683. Although the claims at issue are not identical, they are not patentably distinct from each other because current application claims similar features as the issued patent. The current application claims similar features such as a first external input node to receive a first external supply voltage in the first and second conversion-efficiency modes; a second external input node to receive a second external supply voltage in the first conversion-efficiency mode, the second external supply voltage absent from the second external input node in the second conversion-efficiency mode; and an internal power supply coupled to the first and second external input nodes and including an internal supply node to provide an internal supply voltage, the internal power supply to provide the internal supply voltage from the second external supply voltage in the first conversion-efficiency mode and to derive the internal supply voltage from the first external supply voltage in the second conversion-efficiency mode.
Allowable Subject Matter
Currently, claims 2-21 are rejected under double patenting rejection. The claims would be allowable if the double patenting rejection is overcame.
The following is a statement of reasons for the indication of allowable subject matter:
After further search and consideration it is determined that the prior art of record neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach, the following limitation(s) in combination with the remaining claimed limitation:
With regards to claim 2, a second external input node to receive a second external supply voltage in the first conversion-efficiency mode, the second external supply voltage absent from the second external input node in the second conversion-efficiency mode; and an internal power supply coupled to the first and second external input nodes and including an internal supply node to provide an internal supply voltage, the internal power supply to provide the internal supply voltage from the second external supply voltage in the first conversion-efficiency mode and to derive the internal supply voltage from the first external supply voltage in the second conversion-efficiency mode.
With regards to claim 12, a second external input node to receive a second external supply voltage in the first conversion-efficiency mode, the second external supply voltage absent from the second external input node in the second conversion-efficiency mode; an internal power supply coupled to the first and second external input nodes and including an internal supply node to provide an internal supply voltage, the internal power supply to provide the internal supply voltage from second external supply voltage in the first conversion-efficiency mode and to derive the internal supply voltage from the first external supply voltage in the second conversion-efficiency mode; and a voltage converter to produce a third external supply voltage from the first external supply voltage and the internal supply voltage in both the first and second conversion-efficiency modes.
With regards to claim 18, distinguishing between a presence of a second external supply voltage and an absence of the second external supply voltage; in the presence of the second external supply voltage, deriving a third supply voltage from the second external supply voltage and the first external supply voltage; in the absence of the second external supply voltage, deriving the third supply voltage from the first external supply voltage; and distributing the third supply voltage to the memory devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824