DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Liao (US 20210327882 A1) in view of Liu (US 20240040778 A1)
Regarding Claim 1: Liao teaches a semiconductor structure, comprising:
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A substrate including a plurality of pillars (See annotated figure 11 below for pillars) in an array region of the substrate (The array region being the region where the pillars are located), wherein a top surface of each of the plurality of pillars is a substantially planar surface (See annotated figure 11 below);
An oxide layer, surrounding each of the pillars (601 is an insulating film that is on top of the pillars, therefore surrounds each of the pillars on the top, as seen in Fig. 11. Paragraph 203 explains another insulating layer being silicon oxide);
A plurality of word lines, disposed in the pillars respectively (221 inside of pillar 209 – Fig 10 which shows a zoomed in pillar); and
A plurality of contacts (109A and 109B), wherein each contact is disposed between two adjacent pillars (either of 109A and 109B are located in between the pillars, see annotated fig 11 above for the pillars).
Wherein each of the word lines includes a dielectric layer (203, Paragraph 58 states that this insulating layer includes an oxide layer, which is a dielectric material), a lower electrode structure (205), and an upper electrode structure (219); the dielectric layer is disposed in the respective pillar, the lower electrode structure is disposed on the dielectric layer, and the upper electrode structure is disposed on the lower electrode structure (Figure 10 shows the lower electrode structure, 205, on top of the dielectric layer, 203, and the upper electrode structure, 219, on top of the lower electrode structure, 205).
Liao does not explicitly teach wherein the insulating layer surrounding each of the pillars is an oxide layer (noting that Liao does not specifically disclose the material of insulating layer 601), a residual film, partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars.
Liao discloses other insulating layers that are made out of oxide (paragraph 73, paragraph 81).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Liao to include wherein layer 601 is an oxide in order to provide a strong bond with the connecting layers as well as having a high dielectric strength, which will help increase the stability and longevity of the semiconductor device.
Liao as modified still lacks a residual film, partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars.
Liu teaches a residual film, partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars (2230 is a third dielectric material layer that partially covers the sidewalls of the pillars, 100- See Fig 10B, paragraph 119 noting that inside the pillar there is still a lower dielectric layer 222 that would be on the bottom of the pillar and be similar to the lower dielectric layer inside the pillar in Liao)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liao to add a residual film, partially disposed on the sidewalls, as taught by Liu, because the residual film acts as buff between the sidewalls of the pillar and the subsequent deposited material, which reduces the chance of delamination and other defects.
Regarding claim 2, Liao, as modified, teaches the upper electrode structure (219, Figure 10 shows the layers inside the upper electrode structure) includes a preliminary source layer (211), a preliminary work-function adjustment layer (215), and a conductive layer (217), the preliminary source layer is disposed on the lower electrode structure and a sidewall of the dielectric layer (Figure 10 shows the lower preliminary source layer on top of the lower electrode structure, 205, and in contact with the dielectric layer, 203, on its sides), the preliminary work-function adjustment layer conformally covers the preliminary source layer (Fig 10 shows the work-function adjustment layer, 215, covering the preliminary source layer, 211), and the conductive layer covers substantially an entire surface of the preliminary work-function adjustment layer opposite the preliminary source layer (Fig 10 shows the conductive layer, 217, on top of the work-function adjustment layer, 215, which is on top of the preliminary source layer, 211).
Regarding claim 3, Liao, as modified, teaches the word lines and the contacts are alternately arranged (Fig 11 shows the contacts, 109A and 109B, being alternatively arranged with the pillars)
Regarding claim 4, Liao, as modified teaches the semiconductor structure of claim 1, wherein the substrate includes a peripheral region surrounding the array region, and the residual film is disposed in the peripheral region (The residual film comes from the modifications to Liao in regards to Liu already made in claim 1. As the array region is the region in which the pillars are located in, that the part of the substrate outside of and surrounding the pillars and on the periphery would be considered the peripheral region therefore the residual film being on the outside of the pillars would be considered part of the peripheral region.)
Regarding claim 5, Liao et al., as modified, teaches a nitrogen treatment is performed on the substrate (Paragraph 0062 describes nitrogen being generated and being added to the substrate, which achieves the same structural result as a nitrogen treatment. Note this is process limitation in a product claim, which is only limited by the structure implied by the steps – MPEP 2113.)
Regarding claim 6, Liao et al, as modified, teaches the nitrogen treatment being to provide nitrogen to the substrate (Paragraph 0062 describes how Nitrogen is added to the substrate. It is known that a nitrogen treatment would add nitrogen to the substrate. Note this is process limitation in a product claim, which is only limited by the structure implied by the steps – MPEP 2113.)
Regarding claim 7, Liao, as modified, doesn’t explicitly teach the residual film capping each of the pillars.
Liu teaches the residual film capping each of the pillar (2230 is shown in Fig 10B to be covering the tops of the pillars)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liao to have the residual layer cap the top of the pillars, as taught by Liu, because the presence of a residual film layer capping the pillars serves to protect the pillars, reducing the risk of defects, which is critical to semiconductor performance.
Regarding claim 8, Liao, as modified, teaches the preliminary source layer formed using a chemical vapor deposition (CVD) process (Paragraph 0059).
Regarding claim 9, Liao, as modified, teaches the preliminary source layer including a work-function adjustment element or a compound of the work-function adjustment element (Paragraph 0059).
Regarding claim 10, Liao, as modified, teaches the conductive layer including a low-resistance material having a resistance less than that of the preliminary work-function adjustment layer (Paragraph 63 teaches that the conductive layer is made out of material that is less resistive than that of the preliminary diffusion layer, 213. Paragraph 0061 further teaches that the preliminary diffusion layer is completely formed into the preliminary work-function layer, 215. Meaning that 213 and 215 would be out of the same material, therefore, the preliminary-work function layer would be made out of material more resistive than the conductive layer).
Regarding claim 11, Liao, as modified, teaches the top surfaces of the source layer, the work-function adjustment layer and the conductive layer formed by an etching process are disposed at a same level (Paragraph 0064)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Oyu (US 20080258209 A1) shares a similar structure, specifically in regards to having a film that only partially covers the sides of a set of pillars.
Hsieh (US 20230253209 A1) has a series of pillar-like structure above word lines and shares a nitrogen treatment that adds nitrogen to the substate.
Kim et al. (US 20240032287 A1) has buried contacts disposed between a series of pillars along with containing word lines in said pillars, which form an alternating pattern with the contacts.
Park et al. (US 20220189968 A1) contains a series of pillars along with multiple word lines which is divided into an upper and a lower part.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLOTTE ELIZABETH HARBOTTLE whose telephone number is (571)270-0644. The examiner can normally be reached Monday-Friday 7:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.E.H./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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