DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 12-14 objected to because of the following informalities:
Claims 12 and 13 still contain numbers from the specifications for the insulating layer. In both of these claims “insulating layer 14” should be changed to “insulating layer”, removing the reference numbers.
Within claim 14, it is suggested that in line 2 “a plurality of trenches from in the pillars” is changed to “a plurality of trenches for the pillars” as the phrasing of this sentence could be clearer grammatically.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 claims a structure in which the residual film caps each of the pillars. However, that limitation contradicts claim 1, which claim 7 is dependent on, which states that the top surface of the residual film is coplanar with the top surface of the pillars. These two limitations cannot exist at the same time, therefore claim is unclear how these two limitations could exist at the same time.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190027480 A1) in view of Kim et al. (US 20200082858 A1).
Regarding the amended claim 1, Lee et al. teaches a semiconductor structure, comprising:
a substrate, including a plurality of pillars (200 and 260 in Figure 2A) in an array region (The array region being the region where the pillars are located) of the substrate (Paragraph 0025 describes the pillars, each pillar consists of 200, 210, and 260, within the substrate, 100), wherein a top surface of each of the plurality of pillars is a substantially planar surface (Figure 2A shows that the top surfaces of each of the pillars are planar surfaces);
an oxide layer, surrounding each of the pillars, a top surface of each of the pillars is exposed from the oxide layer (Fig 2A shows that a separation, 101, member surrounds the pillars, 200, 210, and 260. Paragraph 0053 describes that the separation member, 101, is made out of silicon oxide);
a plurality of word lines, disposed in the pillars respectively (Paragraph 0025 describes that trenches include word lines, 200); and
a plurality of contacts, wherein each contact is disposed between two adjacent pillars (Fig 2A shows contacts, 310 and 320, in between two adjacent pillars, 200, 210, and 260);
wherein each of the word lines includes a dielectric layer, a lower electrode structure, and an upper electrode structure (Fig 2A shows that the word lines, 200, consists of a insulating layer, 210, a lower electrode structure, G1, and an upper electrode structure, G2); the dielectric layer is disposed in the respective pillar (Fig 2A shows that the insulating layer, 210 and 260, is within the pillar – noting that 260 may be a dielectric/oxynitride paragraph 67 and 210 may be an oxynitride), the lower electrode structure is disposed on the dielectric layer (Fig 2A shows that the lower electrode structure, G1, is on the dielectric layer), and the upper electrode structure is disposed on the lower electrode structure (Fig 2A shows the upper electrode structure, G2, on top of the lower electrode structure, G1);
wherein a top surface of the dielectric layer and the top surfaces of the pillars are coplanar (Fig 2A shows that the top of the pillars, 200, 210, and 260, and the top surface of the dielectric layer, top of 260, are coplanar with each other).
Lee et al. does not teach a residual film, partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars wherein the top surface of the residual film is coplanar with the top surfaces of the oxide layer and the pillars (This not being taught because of the lack of a residual layer within Lee et al).
Kim et al. teaches a residual film, partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars (Fig 16, shows a gate spacer, 33, which serves as a residual layer that is formed on the sidewalls of the pillar structure, which consists of 26, 29, and 35) wherein the top surface of the residual film is coplanar with the top surfaces of the oxide layer and the pillars (In Fig. 16 the residual layer, 33, is shown to be coplanar with the top of the pillar, 35, and a silicon oxide layer, 37).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. to add a residual film partially disposed on the sidewalls and coplanar with the surface of the oxide layer the pillars, as taught by Kim et al., because the residual film acts as a buffer between the sidewalls of the pillar and the subsequent deposited material, which reduces the chance of delamination and other defects. Furthermore, making the residual film coplanar with the oxide layer and the pillars helps to ensure uniformity across the semiconductor structure.
Regarding claim 2, Lee et al., as modified, teaches that the upper electrode structure includes a preliminary source layer, a preliminary work-function adjustment layer, and a conductive layer (Fig 3A shows that the upper electrode, G2, contains a source layer, 220, a work-function adjustment layer, 235, and a conductive layer, 250), the preliminary source layer is disposed on the lower electrode structure and a sidewall of the dielectric layer (Fig 2A shows that the source layer, 220, is on the lower electrode structure, G1, and surrounding the sidewalls of the dielectric layer, 210), the preliminary work-function adjustment layer conformally covers the preliminary source layer (Fig 2A shows the work-function adjustment layer, 235, cover the source layer, 220), and the conductive layer covers substantially an entire surface of the preliminary work-function adjustment layer opposite the preliminary source layer (Fig 2A shows the conductive layer, 250, on top of the work-function adjustment layer, 235, which is on top of the source layer, 220).
Regarding claim 3, Lee et al., as modified, teaches that the word lines and the contacts are alternately arranged (Fig 2A shows the word lines, 200, alternately arranged with the contacts, 310)
Regarding the amended claim 4, Lee et al., as modified, teaches the substrate including a peripheral region surrounding the array region, and the residual film is disposed in the peripheral region (The residual layer comes from the modifications to Lee in regards to Kim made in claim 1. As the array region is the region in which the pillars are located in, that the part of the substrate outside of and surrounding the pillars and on the periphery would be considered the peripheral region therefore the residual film being on the outside of the pillars would be considered part of the peripheral region), wherein the oxide layer contacts a lower portion of a sidewall of each of the pillars below the residual film, such that an upper portion of the sidewall of each of the pillars is separated from the oxide layer by the residual film (As the residual layer from Kim et al. taught in for claim 1, which this claim is dependent on, does not cover the bottom of the pillars, the oxide layer, 101, would cover the lower portions of the pillars while the residual film would separate the oxide layer from the upper sidewalls of the pillars).
Regarding claim 5, Lee et al., as modified, teaches wherein a nitrogen treatment is performed on the substrate (Paragraph 0063 describes a treatment process on the work-function element which decomposes. Paragraph 0064 describes that after the decomposing of the work-function element, it diffuses into the lower electrode structure, G1, which is within the word lines, 200. Paragraph 0025 describes the word lines, 200, as being in the substrate, 100. Note this is a process limitation in a product claim, which is only limited by the structure implied by the steps – MPEP 2113, a nitrogen treatment does not result in any structural difference, therefore the structure of the prior art is configured such as a nitrogen treatment may be performed on it).
Regarding claim 6, Lee et al., as modified, teaches the nitrogen treatment is to provide nitrogen to the substrate (Paragraph 0064 describes nitrogen being add to the lower electrode structure, G1, which is part of the word lines, 200. Paragraph 0025 explains that the word lines, 200, are in the substrate. Therefore, nitrogen is being add to the substrate. It is known that a nitrogen treatment would add nitrogen to the substrate. Note this is process limitation in a product claim, which is only limited by the structure implied by the steps – MPEP 2113).
Regarding claim 8, Lee et al., as modified, teaches the that the preliminary source layer is formed using a chemical vapor deposition (CVD) process (Paragraph 0059 describes the preliminary source layer formed using chemical vapor deposition. Note this is process limitation in a product claim, which is only limited by the structure implied by the steps – MPEP 2113).
Regarding claim 9, Lee et al., as modified, teaches the preliminary source layer including a work-function adjustment element or a compound of the work-function adjustment element (Paragraph 0028 describes the source layer, 220, containing a work-function adjustment element).
Regarding claim 10, Lee et al., as modified, teaches that the conductive layer includes a low-resistance material having a resistance less than that of the preliminary work- function adjustment layer (Paragraph 0030 describes the conductive layer, 250, having a lower resistance than the work-function adjustment layer, 235).
Regarding claim 11, Lee et al., as modified, top surfaces of the source layer, the work-function adjustment layer and the conductive layer formed by an etching process are disposed at a same level (Paragraph 0031 describes the top surfaces of the source layer, the work-function adjustment layer, and the conductive layer disposed at the same level).
Regarding the added claim 12, Lee et al., as modified, teaches an insulating layer formed on a top surface of the oxide layer and the top surface of each of the pillars (Fig 2A shows an insulating layer, 400, on the top surfaces of the oxide layer, 101, and each of the pillars, 260 being the top surface of the pillar).
Regarding the added claim 13, Lee et al., as modified, teaches the insulating layer in contact with the vertical portions of the residual film. (As Kim et al. taught in that the residual film is coplanar with the top surface of the pillars and the oxide layer, which Figure 2A shows the insulating layer being in contact with both those layers, then the residual layer will also be in contact with the insulating layer).
Regarding the added claim 14, Lee et al., as modified, teaches the substrate further comprising a plurality of trenches from in the pillars and extended through the insulating layer, wherein each of the trenches has an opening formed at the insulating layer and is surrounded by the oxide layer (Fig 10A shows that the trenches, 120, are located within the pillars. The trenches, 120, are surrounded by the oxide layer, 101, and the top of the opening for the trench is where the insulating layer would be located).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190027480 A1) in view of Kim et al. (US 20200082858 A1) as applied to claim 1 above, and further in view of Liu (US 20240040778 A1).
Regarding claim 7, Lee et al., as modified, does not explicitly teach the residual film capping each of the pillars.
Liu teaches the residual film capping each of the pillars (2230, which is made out of dielectric material, like 33 in Kim et al., is shown in Fig 10B to be covering the tops of the pillars)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. in view of Kim et al. to have the residual layer cap the top of the pillars, as taught by Liu, because the presence of a residual film layer capping the pillars serves to protect the pillars, reducing the risk of defects, which is critical to semiconductor performance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
As a new reference was found in regards to the amendments to the claims, the remarks on the arguments made in the non-final rejection are no longer relevant to the above rejections, with the prior art only being used as secondary references for dependent claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLOTTE ELIZABETH HARBOTTLE whose telephone number is (571)270-0644. The examiner can normally be reached Monday-Friday 7:30-5.
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/C.E.H./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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