DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The reply filed on 9/8/2026 is not fully responsive to the prior Office action because of the following omission(s) or matter(s): The double patenting rejection is not addressed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-13 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-6 and 8-15 of U.S. Patent No. 12046620 in view of Kameshima.
As to claim 1 ‘620 claim 1 teaches An optical semiconductor device, comprising: a logic die comprising: a core circuit area and a logic peripheral circuit area located adjacent thereto; a memory die positioned on the logic die and comprising: a memory cell area positioned on the core circuit area and a memory peripheral area positioned on the logic peripheral circuit area; and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area, wherein the first inter-die via has a back end extended to a back surface of the memory die and a front end extended through a front surface of the memory die to the logic die; an intervening structure disposed on the memory die; and a sensor die positioned on the memory die and comprising: a sensor pixel area positioned on the memory cell area and a sensor peripheral area positioned on the memory peripheral area; a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, wherein the first intra-die via has a back end extended to a back surface of the sensor die and a front end extended to a front surface of the sensor die; and a second intra-die via positioned in the sensor peripheral area, wherein the second intra-die via has a back end extended to the back surface of the sensor die and a front end extended toward the front surface of the sensor die; wherein the intervening structure is formed between the back surface of the memory die and the front surface of the sensor die; wherein a height of the first intra-die via is greater than a height of the second intra-die via.
Recitation of wherein the second intra-die via is electrically connected to a conductive line of the sensor die can be found in claim 6 but not in claim 1
Recitation of wherein the first intra-die via is topographically aligned with the first inter-die via and directly positioned on the first inter-die via is not taught.
Kameshima teaches of wherein the second intra-die via is electrically connected to a conductive line of the sensor die ( 157a connected to lines in 105 figure 7a)
Kameshima also teaches wherein the first intra-die via is aligned with the first inter-die via and directly positioned on the first inter-die via is not taught (157b and 157 a in figure 7a -7e aligned does not mean they are overlap or vertically aligned the broadest reasonable interpretation In agreement or positioned relational IT is noted Kameshima goes further and teaches overlap between 157a and 157b (figure 7A and 7E and 9B)
Thus it would have been obvious to one of ordinary skill in the art at the time of filing to provide the second intra-die via is electrically connected to a conductive line of the sensor die to provide electrical communication within the die as well as use conventional alignment of vias an interconnect to provide known and expected outcomes and to provide the first intra-die via is aligned with the first inter-die via and directly positioned on the first inter-die via to allow communication and interconnection between the dies use conventional alignment of vias an interconnects to provide expected and known outcomes.
The claims in the instant of application are broader since they do not include wherein a height of the first intra-die via is greater than a height of the second intra-die via;
b. As to claim 2, recitation of wherein the intervening structure includes a first layer positioned on the memory die, a second layer positioned on the first layer, and a third layer positioned on the second layer. is verbatim of claim 2 of ’620 since ‘620 is more specific.
c. As to the recitation of claim 3, wherein the first layer and the second layer are formed of a first material, while the second layer is formed of a second material different from the first material this is found verbatim in claim 3 of ‘620.
d. As to the recitation of claim 4, wherein the first layer is formed of silicon oxide or silicon nitride, the second layer is formed of silicon, and the third layer is formed silicon oxide or silicon nitride this is verbatim in claim 4 of ‘620.
e. As to claim 5, recitation of wherein the first intra-die via and the second intra-die via are electrically coupled is found verbatim in claim 5 of ‘620.
f. As to claim 6, recitation of wherein the sensor die comprises: a dielectric layer positioned on the memory die; a substrate positioned on the dielectric layer of the sensor die; and a sensor unit positioned in the substrate of the sensor die; wherein the first intra-die via is positioned penetrating along the substrate of the sensor die and the dielectric layer of the sensor die (is found verbatim in claim 8 of ‘620.
g. As to claim 7,recitation of further comprising a transfer gate positioned in the dielectric layer of the sensor die is found verbatim in claim 9 of ‘620.
h. As to claim 8, recitation of further comprising a floating diffusion unit positioned in the substrate of the sensor die and positioned in a drain of the transfer gate is found verbatim in claim 10 of ‘620.
i. As to claim 9, recitation of further comprising a color filter positioned on the substrate of the sensor die and above the sensor unit is found verbatim in claim 11 of ‘620.
j. As to claim 10, recitation of further comprising a micro-lens positioned on the color filter is found verbatim in claim 12 of ‘620.
k. As to claim 11, recitation of further comprising an upper layer positioned between the color filter and the substrate of the sensor die; wherein the upper layer comprises a bottom anti-reflective coating is found verbatim in claim 13 of ‘620.
l. As to claim 12, recitation of wherein a height ratio of a height of the first intra-die via to a height of the second intra-die via is between about 10:3 and about 5:4 is found verbatim in claim 14.
m. As to claim 13, recitation of wherein the first inter-die via comprises: a filler layer positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and an isolation layer covering two sidewalls of the filler layer is found verbatim in claim 15.
Response to Arguments
Applicant's arguments filed 9/8/2026 have been fully considered but they are not persuasive. Applicant has not addressed all the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F. Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
Prosecution Insights