DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim 1 of the instant of application is the same as original claims 6 and 7 of parent application 17/551,427. The office had already provided a rejection for claim 7 if applicant had placed original claims 6 7 in independent form in the manner provided the office would the next action as a final rejection. Applicant provides no explanation as to deficiencies in the rejection provided in the office action dates 4/4/2024 of claims 6 and 7 in the application of 17/551,427 thus this action could be final under MPEP 706.07b.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The recitation of topological aligned is unclear. Topological refers to either the way parts are integrated or the geometric properties.
In the first definition the term topological aligned does not make sense since topology refers to integration of the parts thus topologically aligned means align in a integration manner but there is no integration aspects set form. The second definition is not clear since the geometries are different. It appears applicant means they are simply aligned.
wherein the second intra-die via is electrically connected to a conductive line of the sensor die. It is unclear if the sensor has a conductive line since it is not positively recited it appears to be conditional
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kameshima 20210104572 in view of Nojima 9419040 both cited in the parent.
a. As to claim 1-3, Kameshima teaches An optical semiconductor device, comprising: a logic die comprising: a core circuit area and a logic peripheral circuit area (110C center/core potion with elements figure 6-9 and peripheral region with via 157b core vs periphery is not limiting without specific structure the region can be arbitrarily defined to have a core and a periphery ); a another die positioned on the logic die and comprising: a second die with a core/cell area and a memory peripheral area (110b same correspondence was 110C likewise the core are arbitrary the without some structure to limit the region can be) ; and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area (item 157b); and a sensor die positioned on the memory die and comprising (110a): a sensor pixel area (region with 111) and a sensor peripheral area (region without 111; a first intra-die via (the longer of the 157a) s positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via (155a and the sensor is connected to the logic via 157b and 157a) ; and a second intra-die via positioned in the sensor peripheral area (the shorter of the 157as); wherein a height of the first intra-die via is greater than a height of the second intra-die via (by definition). Mitsuhashi teaches a color filter (111) and micro lens (113 ) on the sensor die substrate (claims 11 and 12 limitations). Kameshima teaches wherein the second intra-die via is electrically connected to a conductive line of the sensor die (see figures the vias is connected to lines in the sensor). Kameshima teaches wherein the first intra-die via is topographically aligned (sic aligned) with the first inter-die via and directly positioned on the first inter-die via (see figures 7a and 9).
Kameshima does not teach an intervening structure disposed on the memory die or 110b us a memory dies where the center is a cell and the outer is a peripheral region.
With regards to the memory Mitsuhashi does not limit whether 110a is the memory and 110b is the logic or 110b is the memory and 110a is the logic. However, there is in no show of unexpected results of the configuration. Thus, it would have been obvious to one of ordinary skill in the art at the time of filling to provide 110a as a logic and 1110b as a memory where the active or center portion is a cell and the outer portion is a periphery area of the memory in for the desired design parameters of the device.
In reJapikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
With respect to the to the intervening structure Nojima teaches providing a 3-layer intervening structure with (a first insulating material 94 and second insulating film 95 and a first insulating film 84) Further each of 84 95 and 94 can be multi layers.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide a multilayer laminate to reduce stress during bonding and to provide isolation between device.
b. As to claim 4, Nojima teaches silicon nitride/silicon oxide/silicon nitride. It is noted silicon oxide is formed from silicon.
c. As to claim 5, Kameshima teaches herein the first intra-die via and the second intra-die via are electrically coupled (see figures).
d. As to claim 6, Kameshima teaches wherein the sensor die comprises: a dielectric layer positioned on the memory die (103); a substrate positioned on the dielectric layer of the sensor die(101); and a sensor unit positioned in the substrate of the sensor die (paragraph 252); wherein the first intra-die via is positioned penetrating along the substrate of the sensor die and the dielectric layer of the sensor die (see figures).
e. As to claim 7-8, Kameshima teaches transfer transistors and floating regions associated with each PD (figures 26 and 27) but does not appear to explicitly teach the transfer gate positioned in the dielectric layer of the sensor die and the floating diffusion unit positioned in the substrate of the sensor die and positioned in a drain of the transfer gate.
However, these configurations are known and applicant has shown no unexpected results for the orientation . Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the transfer gate positioned in the dielectric layer of the sensor die and the floating diffusion unit positioned in the substrate of the sensor die and positioned in a drain of the transfer gate to provide an backside sensor with optimized performance for charge transfer.
f. As to claims 9-10, Kameshima wherein the sensor unit, the color filter, and the micro-lens are aligned/on the color filter (sic aligned see figures and item 113 relative to 111).
g. As to claim 11 Kameshima teaches , further comprising an upper layer positioned between the color filter and the substrate of the sensor die; wherein the upper layer comprises a bottom anti-reflective coating (item 109). Applicant does not give a degree of anti-reflection however applicant list SiO as an anti-reflective material which is taught in paragraph 279.
h. As to claim 12, Kameshima does not explicitly teach wherein a height ratio of a height of the first intra-die via to a height of the second intra-die via is between about 10:3 and about 5:4.
However, applicant has shown no unexpected results. Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide wherein a height ratio of a height of the first intra-die via to a height of the second intra-die via is between about 10:3 and about 5:4 to optimize the thickness of the dies and the current that can withstood in each via.
i. As to claim 13, Kameshima Mitsuhashi teaches at the first inter-die least a filler but does not teach an insulation layer on the sidewalls (figure 75 the vias are fillet with a metal).
However, isolation barriers to prevent metal diffusion from the filler are known in the art at the time of filing.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the vias with a filler and an outer diffusion barrier/isolation to prevent undesired out diffusion of the filler to surrounding circuitry,
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-13 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-6 and 8-15 of U.S. Patent No. 12046620 in view of Kameshima.
As to claim 1 ‘620 claim 1 teaches An optical semiconductor device, comprising: a logic die comprising: a core circuit area and a logic peripheral circuit area (verbatim); a memory die positioned on the logic die and comprising: a memory cell area and a memory peripheral area; and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area ( verbatim and more specific since it link the cell area to the core and the peripheral areas; an intervening structure disposed on the memory die (verbatim); d a sensor die positioned on the memory die and comprising: a sensor pixel area and a sensor peripheral area ( verbatim and more specific since it links the positions); a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via ( verbatim and more specific); and a second intra-die via positioned in the sensor peripheral area (verbatim and more specific); wherein a height of the first intra-die via is greater than a height of the second intra-die via (verbatim);
Recitation of wherein the second intra-die via is electrically connected to a conductive line of the sensor die can be found in claim 6 but not in claim 1
Recitation of wherein the first intra-die via is topographically aligned with the first inter-die via and directly positioned on the first inter-die via is not taught.
Kameshima teaches of wherein the second intra-die via is electrically connected to a conductive line of the sensor die ( 157a connected to lines in 105 figure 7a)
Kameshima also teaches wherein the first intra-die via is aligned with the first inter-die via and directly positioned on the first inter-die via is not taught (157b and 157 a in figure 7a -7e aligned does not mean they are overlap or vertically aligned the broadest reasonable interpretation In agreement or positioned relational IT is noted Kameshima goes further and teaches overlap between 157a and 157b (figure 7A and 7E and 9B)
Thus it would have been obvious to one of ordinary skill in the art at the time of filing to provide the second intra-die via is electrically connected to a conductive line of the sensor die to provide electrical communication within the die as well as use conventional alignment of vias an interconnect to provide known and expected outcomes and to provide the first intra-die via is aligned with the first inter-die via and directly positioned on the first inter-die via to allow communication and interconnection between the dies use conventional alignment of vias an interconnects to provide expected and known outcomes.
b. As to claim 2, recitation of wherein the intervening structure includes a first layer positioned on the memory die, a second layer positioned on the first layer, and a third layer positioned on the second layer. is verbatim of claim 2 of ’620 since ‘620 is more specific.
c. As to the recitation of claim 3, wherein the first layer and the second layer are formed of a first material, while the second layer is formed of a second material different from the first material this is found verbatim in claim 3 of ‘620.
d. As to the recitation of claim 4, wherein the first layer is formed of silicon oxide or silicon nitride, the second layer is formed of silicon, and the third layer is formed silicon oxide or silicon nitride this is verbatim in claim 4 of ‘620.
e. As to claim 5, recitation of wherein the first intra-die via and the second intra-die via are electrically coupled is found verbatim in claim 5 of ‘620.
f. As to claim 6, recitation of wherein the sensor die comprises: a dielectric layer positioned on the memory die; a substrate positioned on the dielectric layer of the sensor die; and a sensor unit positioned in the substrate of the sensor die; wherein the first intra-die via is positioned penetrating along the substrate of the sensor die and the dielectric layer of the sensor die (is found verbatim in claim 8 of ‘620.
g. As to claim 7,recitation of further comprising a transfer gate positioned in the dielectric layer of the sensor die is found verbatim in claim 9 of ‘620.
h. As to claim 8, recitation of further comprising a floating diffusion unit positioned in the substrate of the sensor die and positioned in a drain of the transfer gate is found verbatim in claim 10 of ‘620.
i. As to claim 9, recitation of further comprising a color filter positioned on the substrate of the sensor die and above the sensor unit is found verbatim in claim 11 of ‘620.
j. As to claim 10, recitation of further comprising a micro-lens positioned on the color filter is found verbatim in claim 12 of ‘620.
k. As to claim 11, recitation of further comprising an upper layer positioned between the color filter and the substrate of the sensor die; wherein the upper layer comprises a bottom anti-reflective coating is found verbatim in claim 13 of ‘620.
l. As to claim 12, recitation of wherein a height ratio of a height of the first intra-die via to a height of the second intra-die via is between about 10:3 and about 5:4 is found verbatim in claim 14.
m. As to claim 13, recitation of wherein the first inter-die via comprises: a filler layer positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and an isolation layer covering two sidewalls of the filler layer is found verbatim in claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
Prosecution Insights