DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 26, 2026 has been entered.
Status of the Claims
Species 6, as shown in FIGs. 26-27, was elected.
Amendment filed January 26, 2026 is acknowledged. Claims 1, 2, 6, 9, 11, 15 and 19 have been amended. Claims 1-4, 6-13, 15-19 and 21-23 are pending.
Action on merits of the Elected Species 6, claims 1-4, 6-13, 15-19 and 21-23 follows.
Specification
Cancelation of subject matter added to paragraph [0115] is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-4, 6-13, 15-19 and 21-23 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “each adjacent pair of the first body ring, the second body ring, the third body ring, and the fourth body ring is completely separated from one another only by a first portion of the epitaxial layer” (amended claims 1 and 11)” (emphasis added) in the application as filed.
Applicant must cancel the un-support new matters in response to the Office Action.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-4, 6-13, 15-19 and 21-23 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “each adjacent pair of the first body ring, the second body ring, the third body ring, and the fourth body ring is completely separated from one another only by a first portion of the epitaxial layer” (amended claim 1) is a negative limitation that rendered the claim indefinite because it was an attempt to claim the invention by excluding what the inventor did not invent rather than distinctly and particularly pointing out what they did invent. See In re Schechter, 205 F.2d 185, 98 USPQ 144 (CCPA 1953). (See MPEP 2173.05(i)). Any negative limitation or exclusionary proviso must have basis in the original disclosure. See In re Johnson, 558 F.2d 1008, 1019, 194 USPQ 187, 196 (CCPA 1977).
Therefore, claims 1, 11 and all dependent claims are indefinite.
Amended claims 1 and 11 recite: “the first portion of the epitaxial layer extending continuously from a top surface of the body ring structure to a bottom surface of the body ring structure” and “the second portion of the epitaxial layer extends continuously from a top surface of the body ring structure to a bottom surface of the body ring structure”.
Since the same limitation “the epitaxial layer extending (or extends) continuously from a top surface of the body ring structure to a bottom surface of the body ring structure” being identified with two different names “first portion” and “second portion”, the claim is indefinite.
Therefore, claims 1, 11 and all dependent claims are indefinite.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4, 9-13, 19, 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over HISAMOTO (US. Pub. No. 2002/0088991) of record, in view of SAITOH et al. (US. Pub. No. 2002/0185705) both of record.
With respect to claim 1, As best understood by the Examiner, HISAMOTO teaches a method substantially as claimed including:
growing an epitaxial layer (n-) over a substrate;
forming a plurality of gates in the epitaxial layer (n-), wherein the plurality of gates comprises a first gate trench (TR, not shown), a second gate trench (TR), and a third gate trench (TR, right);
forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer (n-), comprising a reduced surface field (RESURF) structure (20), wherein the step of forming the breakdown voltage enhancement and leakage prevention structure in the epitaxial layer comprises:
forming the RESURF structure (20) in the epitaxial layer (n-), wherein a sidewall of the RESURF structure (20) is in direct contact with a sidewall of the third gate trench (TR, right), and wherein a second portion of the epitaxial layer (n-) is disposed below the RESURF structure (20) and is in contact with the sidewall of the third gate trench (TR, right), and a bottom surface of the RESURF structure (20), and wherein the RESURF structure (20) is a continuous layer whose bottom surface is above a first portion and the second portion of the epitaxial layer (n-);
forming a source (15) in the epitaxial layer (n-) and a gate-source Electrostatic Discharge (ESD) diode structure (11) over the epitaxial layer (n-);
forming a source contact (5) connected to the source (15) and a first terminal (1B) of the gate-source ESD diode structure, wherein the source contact is surrounded by the breakdown voltage enhancement and leakage prevention structure;
forming a gate contact (6A) connected to a second terminal (1A) of the gate-source ESD diode structure; and
forming a drain contact (12) on opposing sides of the epitaxial layer (n-) of the source contact. (See FIGs. 2-3).
Thus, HISAMOTO is shown to teach all the features of the claim with the exception of explicitly disclosing forming a body ring structure.
However, SAITOH teaches a method including:
forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer (n-), comprising a reduced surface field (RESURF) structure (46) and a body ring structure (39), wherein the step of forming the breakdown voltage enhancement and leakage prevention structure in the epitaxial layer comprises:
forming the body ring structure (39) in the epitaxial layer (n-), wherein the body ring structure (39) is a concentric ring structure comprising at least a first body ring (39), a second body ring (39), a third body ring (39), and a fourth body ring (39), each being a rectangle having rounded corners, and wherein each adjacent pair of the first body ring, the second body ring, the third body ring, and the fourth body ring is completely separated from one another only by a first portion of the epitaxial layer (n-), the first portion of the epitaxial layer (n-) extending continuously from a top surface of the body ring structure (39) to a bottom surface of the body ring structure; and
forming the RESURF structure (46) in the epitaxial layer (n-), wherein a second portion of the epitaxial layer (n-) is disposed below the RESURF structure (46) and is in contact with a bottom surface of the RESURF structure (46), and a sidewall of the first body ring (39), and wherein the second portion of the epitaxial layer (n-) extends continuously from the top surface of the body ring structure (39) to the bottom surface of the body ring structure, and wherein the RESURF structure (46) is a continuous layer whose bottom surface is above the top surface of the body ring structure (39) and above the first portion and the second portion of the epitaxial layer (n-). (See FIGs. 30, 27A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the breakdown voltage enhancement and leakage prevention structure of HISAMOTO including the body ring structure as taught by SAITOH to achieve high breakdown voltage.
With respect to claim 2, the step of forming the breakdown voltage enhancement and leakage prevention structure in the epitaxial layer of HISAMOTO further comprises: forming the RESURF structure (20) through an implantation process, wherein the RESURF structure (20) is in an upper portion of the epitaxial layer (8), and the RESURF structure (20) and the gate-source ESD diode structure (11) are separated by a dielectric layer (7).
With respect to claim 3, in view of SAITOH, the step of forming the breakdown voltage enhancement and leakage prevention structure in the epitaxial layer further comprises:
forming the body ring structure (39) through an implantation process, wherein the body ring structure (39) is entirely contained within a coverage of the RESURF structure (46) in a top view.
With respect to claim 4, in view of HENNING, the RESURF structure (46) and the body ring structure (39) are configured to disperse an electric field on the gate-source ESD diode structure of HISAMOTO; and the RESURF structure (20) is between the gate-source ESD diode structure (11) and the body ring structure, in view of SAITO.
With respect to claim 9, the source of HISAMOTO, comprises a first source region (15) and a second source region (15), and the step of forming the source in the epitaxial layer comprises:
forming the first source region (15) between the first gate trench (TR) and the second gate trench (TR) of the plurality of gates; and
forming the second source region between the second gate trench (TR) and the third gate trench (TR, left) of the plurality of gates.
With respect to claim 10, the method of HISAMOTO further comprises:
forming a first body region (20) between the first gate trench (14) and the second gate trench (14), and forming a second body region (20) is between the second gate trench (14) and the third gate trench (14);
forming a first source contact plug having a first terminal connected to the source contact (5), and a second terminal connected to the first source region (15) and the first body region (20);
forming a second source contact plug having a first terminal connected to the source contact (5), and a second terminal connected to the second source region (15) and the second body region (20);
forming a gate contact plug having a first terminal connected to the gate contact (6), and a second terminal connected to a second terminal of the gate-source ESD diode structure (11);
forming a third source contact plug having a first terminal connected to the source contact (5), and a second terminal connected to a first terminal of the gate-source ESD diode structure (11); and
forming an interlayer dielectric layer (10) over the epitaxial layer (8), wherein the gate-source ESD diode structure (11) is in the interlayer dielectric layer (10).
With respect to claim 11, HISAMOTO teaches a method substantially as claimed including:
growing an epitaxial layer (n-) over a substrate;
forming a plurality of gates in the epitaxial layer, wherein the plurality of gates comprises a first gate (TR, nots shown), a second gate (TR), and a third gate (TR, right);
forming a body region (p, between gates) in the epitaxial layer;
forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer, comprising a RESURF structure (20), wherein the step of forming the breakdown voltage enhancement and leakage prevention structure in the epitaxial layer comprises:
forming the RESURF structure (20) in the epitaxial layer (n-), wherein a sidewall of the RESURF structure (20) is in direct contact with a sidewall of the third gate (TR, right), wherein a second portion of the epitaxial layer is disposed under the RESURF structure (20) and adjacent to the third gate (TR, right) of the plurality of gates, the second portion of the epitaxial layer being in contact with the sidewall of the third gate (TR, right), and a bottom surface of the RESURF structure (20), and wherein the RESURF structure (20) is a continuous layer whose bottom surface is above the first portion of the epitaxial layer, and the second portion of the epitaxial layer;
forming a source (15) in the epitaxial layer;
forming a gate-source ESD diode structure (3) over the epitaxial layer, wherein the gate- source ESD diode structure comprises a plurality of n-type regions and a plurality of p-type regions arranged in an alternating manner in an interlayer dielectric layer over the epitaxial layer;
forming a source contact connected to the source (15) and a first terminal (1B) of the gate-source ESD diode structure, wherein the source contact is surrounded by the breakdown voltage enhancement and leakage prevention structure;
forming a gate contact (6A) connected to a second terminal (1A) of the gate-source ESD diode structure; and
forming a drain contact (12) on opposing sides of the epitaxial layer (8) of the source contact. (See FIGs. 2-3).
Thus, HISAMOTO is shown to teach all the features of the claim with the exception of explicitly disclosing forming the breakdown voltage enhancement and leakage prevention structure in the epitaxial layer comprising a body ring structure.
However, SAITOH teaches a method including:
growing an epitaxial layer (n-) over a substrate (10);
forming a plurality of gates in the epitaxial layer, wherein the plurality of gates comprises a first gate (not shown), a second gate (not shown), and a third gate;
forming a body region (12) in the epitaxial layer;
forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer, comprising a RESURF structure (46) and a body ring structure, wherein the step of forming the breakdown voltage enhancement and leakage prevention structure in the epitaxial layer comprises:
forming the body ring structure in the epitaxial layer (n-), wherein the body ring structure comprises at least a first body ring (39, left), a second body ring (39), a third body ring (39), and a fourth body ring (39, right), each being a rectangle having rounded corners, and wherein each adjacent pair of the first body ring, the second body ring, the third body ring, and the fourth body ring is completely separated from one another only by a first portion of the epitaxial layer (n-), the first portion of the epitaxial layer (n-) extending continuously from a top surface of body ring structure to a bottom surface of the body ring structure; and
forming the RESURF structure (46) in the epitaxial layer (n-), wherein a second portion of the epitaxial layer (n-) is disposed between and separates the first body ring (39, left) from the third gate of the plurality of gates, the second portion of the epitaxial layer being in contact with a bottom surface of the RESURF structure (46), and a sidewall of the first body ring (39, left), the second portion of the epitaxial layer extending continuously from the top surface of the body ring structure to the bottom surface of the body ring structure, and wherein the RESURF structure (46) is a continuous layer whose bottom surface is above the top surface of the body ring structure, the first portion of the epitaxial layer, and the second portion of the epitaxial layer. (See FIGs. 30, 27A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the breakdown voltage enhancement and leakage prevention structure of HISAMOTO including the body ring structure as taught by SAITO to achieve high breakdown voltage.
With respect to claim 12, the step of forming the breakdown voltage enhancement and leakage prevention structure in the epitaxial layer of HISAMOTO further comprises: forming the RESURF structure (20) through an implantation process, wherein the RESURF structure (20) is in an upper portion of the epitaxial layer, and the RESURF structure (20) and the gate-source ESD diode structure (11) are separated by a dielectric layer (7).
With respect to claim 13, the step of forming the breakdown voltage enhancement and leakage prevention structure, in view of SAITO, further comprises: forming the body ring structure (39) through an implantation process, wherein the body ring structure (39) is a concentric ring structure, the body ring structure (39) being entirely contained within a coverage region of the RESURF structure (46) in a top view.
With respect to claim 19, the source of HISAMOTO comprising a first source region (15) and a second source region (15), and the step of forming the source (15) in the epitaxial layer comprises:
forming the first source region (15) between the first gate (TR, not shown) and a second gate (TR) of the plurality of gates; and
forming the second source region (15) between the second gate (TR) and a third gate (TR, right) of the plurality of gates.
With respect to claim 22, the body region of HISAMOTO comprises a first body region and a second body region, both in the epitaxial layer (n-) and the step of forming the body region comprises:
forming the first body region (p) between the first gate (TR, not shown) and the second gate (TR) of the plurality of gates; and
forming the second body region (p) between the second gate (TR) and the third gate (TR, right) of the plurality of gates.
With respect to claim 23, the method of HISAMOTO further comprises: forming a dielectric layer (7g) at bottoms and sidewalls of the plurality of gates (14).
Claims 6-7 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over HISAMOTO ‘991 and SAITOH ‘705, as applied to claims 4 and 13 above, and further in view of WEYERS et al. (US. Pub. No. 2018/0301537) of record.
With respect to claim 6, the step of forming the gate-source ESD diode structure of HISAMOTO over the epitaxial layer comprises:
forming a plurality of n-type regions and a plurality of p-type regions in an alternating manner in an interlayer dielectric layer (10) over the epitaxial layer, wherein:
the plurality of n-type regions and the plurality of p-type regions comprise a first region (1A), a second region (31), a third region (32), a fourth region (33) and a fifth region (1B) connected in cascade, and wherein
in view of SATOH, the first body ring (39, left) is disposed on a left side of a vertical projection of the fifth region (1A);
the fourth body ring (39, right) is disposed on the right side of a vertical projection of the fourth region (31);
the first region (1A) is connected to the gate contact (6A); and
the fifth region (1B) is connected to the source contact (5).
Note that, the ESD diode structure (11) of HISAMOTO is N-P-N-P-N with the source contact being formed on the left and the gate contact being formed on the right.
Thus, HISAMOTO, in view of SAITO, is shown to teach all the features of the claim with the exception of explicitly disclosing the ESD diode structure being a P-N-P-N-P type.
However, WEYERS teaches a method including:
steps of forming a gate-source ESD diode structure over an epitaxial layer (120) comprises:
forming a plurality of n-type regions and a plurality of p-type regions in an alternating manner in an interlayer dielectric layer (310 over the epitaxial layer (120), wherein:
the plurality of n-type regions and the plurality of p-type regions comprise a first p-type region (314), a first n-type region (318), a second p-type region (316), a second n-type region (318) and a third p-type region (312) connected in cascade, and wherein:
the first p-type region (314) is connected to gate contact (600); and
the third p-type region (312) is connected to the source contact (500). (See FIG. 3B, ¶ [0024]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the gate-source ESD diode structure of HISAMOTO in reversed dopant types as taught by WEYERS for the same intended purpose of forming the gate-source ESD diode structure.
Regarding the ESD diode having “n, n+, p” regions, it is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Moreover, the ESD diode, n-p-n-p-n type or p-n-p-n-p type can be formed regardless of the concentration, hence within the ability of one having ordinary skill in the art.
The location of the gate contact as well as the source contact can be switched, hence gate contact is on the left and source contact is on the right, and is within the ability of the one having skill in the art.
With respect to claim 7, in cross-section view, the body ring structure, in view of SAITO (columns 39), and WEYERS (p-n-p-n-p regions), comprises a first column (39, right), a second column (39), a third column (39), and a fourth column (39, left), and wherein:
a sidewall of the first column (39, right) is vertically aligned with a sidewall of the first region (1A);
a sidewall of the second column (39) is vertically aligned with a sidewall of the second region (31);
a sidewall of the third column (39) is vertically aligned with a sidewall of the third region (32); and
a sidewall of the fourth column (39, left) is vertically aligned with a sidewall of the fourth region (33).
With respect to claim 15, he plurality of n-type regions and the plurality of p-type regions of the gate-source ESD diode structure (11) of HISAMOTO comprises a first region (1A), a second region (31), a third region (32), a fourth region (33) and a fifth region (1B) connected in cascade, and wherein
in view of SATOH, the first body ring (39, left) is disposed on a left side of a vertical projection of the fifth region (1A);
the fourth body ring (39, right) is disposed on the right side of a vertical projection of the fourth region (31);
the first region (1A) is connected to the gate contact (6A); and
the fifth region (1B) is connected to the source contact (5).
Note that, the ESD diode structure (11) of HISAMOTO is N-P-N-P-N with the source contact being formed on the left and the gate contact being formed on the right.
Thus, HISAMOTO is shown to teach all the features of the claim with the exception of explicitly disclosing the ESD diode structure being a P-N-P-N-P type.
However, WEYERS teaches a method including:
forming a gate-source ESD diode structure comprises:
a first p-type region (314), a first n-type region (318), a second p-type region (316), a second n-type region (318) and a third p-type region (312) connected in cascade, and wherein:
the first p-type region (314) is connected to gate contact (600); and
the third p-type region (312) is connected to the source contact (500). (See FIG. 3B, ¶ [0024]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the gate-source ESD diode structure of HISAMOTO in reversed dopant types as taught by WEYERS for the same intended purpose of forming the gate-source ESD diode structure.
Regarding the ESD diode having “n, n+, p” regions, it is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Moreover, the ESD diode, n-p-n-p-n type or p-n-p-n-p type can be formed regardless of the concentration, hence within the ability of one having ordinary skill in the art.
The location of the gate contact as well as the source contact can be switched, hence gate contact is on the left and source contact is on the right, and is within the ability of the one having skill in the art.
With respect to claim 16, in view of SAITOH, the body ring structure comprises a plurality of rectangles having rounded corner, and wherein:
in a cross-sectional view, the plurality of rectangles of the body ring structure (39) comprises a first column (39, left), a second column, a third column, and a fourth column (39, right), and wherein:
a sidewall of the first column (39, right) is vertically aligned with a sidewall of the first region (1A);
a sidewall of the second column (39) is vertically aligned with a sidewall of the second region (31);
a sidewall of the third column (39) is vertically aligned with a sidewall of the third region (32); and
a sidewall of the fourth column (3, left) is vertically aligned with a sidewall of the second (33).
Claims 8, 17-18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over HISAMOTO ‘991, and SAITOH ‘705 as applied to claims 3, 13 and 10 above, and further in view of HSIEH (US. Pub. No. 2010/0224931) of record.
With respect to claim 8, HISAMOTO, in view of SAITO, teaches the method as described in claim 3 above and further including:
forming an interlayer dielectric layer (10) over the epitaxial layer;
forming a plurality of trenches in the interlayer dielectric layer (10);
forming a plurality of region at bottom of respective trenches;
performing a metal deposition process to fill the plurality of trenches to form a plurality of source contact plugs and a gate contact plug; and
forming the source contact (5) and the gate contact (6) through an etching process.
Thus, HISAMOTO and SAITOH are shown to teach all the features of the claim with the exception of explicitly disclosing forming a plurality of p+ regions at bottoms of respective trenches.
However, HSIEH ‘931 teaches a method including:
forming an interlayer dielectric layer (180) over epitaxial layer (104);
forming a plurality of trenches (332) in the interlayer dielectric layer (180);
forming a plurality of p+ regions (118) at bottoms of respective trenches (332);
performing a metal deposition process to fill the plurality of trenches to form a plurality of source contact plugs (223) and a gate contact plug (223); and
forming the source contact (120) and the gate contact (122) through an etching process. (See FIGs. 6F-G).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the source contact plugs of HISAMOTO, in view of SAITOH, further including the plurality of p+ regions at bottoms of respective trenches as taught by HSIEH to reduce contact resistant.
With respect to claim 17, HISAMOTO, in view of SAITOH, teaches the method as described in claim 13 above and further including:
forming a plurality of trenches in the interlayer dielectric layer (10);
forming a plurality of region at bottom of respective trenches;
performing a metal deposition process to fill the plurality of trenches to form a plurality of source contact plugs and a gate contact plug; and
forming the source contact (5) and the gate contact (6) through an etching process.
Thus, HISAMOTO, in view of SAITOH, is shown to teach all the features of the claim with the exception of explicitly disclosing forming a plurality of p+ regions at bottoms of respective trenches.
However, HSIEH ‘931 teaches a method including:
forming an interlayer dielectric layer (180) over epitaxial layer (104);
forming a plurality of trenches (332) in the interlayer dielectric layer (180);
forming a plurality of p+ regions (118) at bottoms of respective trenches (332);
performing a metal deposition process to fill the plurality of trenches to form a plurality of source contact plugs (223) and a gate contact plug (223); and
forming the source contact (120) and the gate contact (122) through an etching process. (See FIGs. 6F-G).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the source contact plugs of HISAMOTO further including the plurality of p+ regions at bottoms of respective trenches as taught by HSIEH to reduce contact resistant.
With respect to claim 18, in view of HSIEH, at least one of the plurality of source contact plugs (223) extends through the interlayer dielectric layer (180), the source (140) and partially through the body region (116);
the source contact (120) is connected to the source (140), the body region (116) and the first terminal of the gate-source ESD diode structure through the plurality of source contact plugs (223);
the gate contact plug (223) extended partially through the interlayer dielectric layer (180); and
the gate contact (122) is connected to the second terminal of the gate-source ESD diode structure through the gate contact plug (223).
With respect to claim 21, HISAMOTO ‘991, in view of SAITO ‘705, teaches the method as described in claim 10 above and further including:
extending the first source contact plug through the interlayer dielectric layer (10);
extending the second source contact plug through the interlayer dielectric layer (10);
extending the third source contact plug through the interlayer dielectric layer (10).
Thus, HISAMOTO, in view of SAITO, is shown to teach all the features of the claim with the exception of explicitly disclosing the source contact plugs extending partially through the body regions and forming a p+ region at the bottom of the contact plugs.
However, HSIEH ‘931 teaches a method including:
extending first source contact plug (223) through an interlayer dielectric layer (180), first source region (140), and partially through first body region (116);
extending second source contact plug (223) through the interlayer dielectric layer (180), the second source region (140), and partially through the second body region (116);
extending third source contact plug (333) through the interlayer dielectric layer (180);
forming a p+ region (118) at the second terminal of each of the first (223), second (223) and third (333) source contact plugs and
forming a p+ region at the second terminal of the gate contact plug (333). (See FIG. 4).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the contact plugs of HISAMOTO extending through the interlayer dielectric layer, source regions, and partially through body regions and forming p+ region at the second terminal of each of the contact plugs as taught by HSIEH ‘931 to assure solid electrical contact between the contact plugs and the contact regions and reduce contact resistant.
Note that, the ESD diode can be formed as p-n-p-n-p instead of n-p-n-p-n.
Therefore, p+ region, instead of n+ regions (148,145), are formed at the second terminal of the third source contact plug (333) and gate contact plug (333).
Response to Arguments
Applicant's arguments filed January 26, 2026 have been fully considered but they are not persuasive.
With respect to claim 1, Applicant asserts:
The Examiner acknowledges that HISAMOTO fails to explicitly disclose forming the breakdown voltage enhancement and leakage prevention structure in the epitaxial layer, comprising the reduced surface field (RESURF) structure and a body ring structure. See Final Office Action, page 4.
However, the correct matter is: HISAMOTO fails to teach a body ring structure.
In view of SATOH, the breakdown voltage enhancement and leakage prevention structure comprises both RESURF and body ring structure.
Since layer 40 comprising same dopant type (n), the same concentration (n-) as drift layer 11, and being epitaxially grown, thus, layers 11 and 40 are considered to be one, epitaxial layer.
Therefore, the breakdown voltage enhancement and leakage prevention structure of SAITOH comprises both RESURF and body ring structure being formed in the “epitaxial layer”.
Applicant argues: The Examiner asserts that SAITO discloses a "body ring structure" corresponding to reference numeral 39. However, SAITO's guard rings 39 do not correspond to the claimed body ring structure.
However, as shown in FIG. 27A, numeral 39 are clearly the “body ring structure”.
The RESURF structure is well known in the art. SAITO explicitly teaches: “The RESURF layer 46 commonly connects the pair of guard rings 39”.
Thus, in view of SAITO, the limitation “the breakdown voltage enhancement and leakage prevention structure in the epitaxial layer, comprising RESURF structure and body ring structure” is met.
Note that, the new limitation “wherein each adjacent pair of the first body ring, the second body ring, the third body ring, and the fourth body ring is completely separated from one another only by a first portion of the epitaxial layer” is an unsupported new matter.
Moreover, between the body ring structure of SAITOH are epitaxial layer (n-). (See FIG. 30).
As shown in the rejection, the sidewall of the RESURF structure 20 of HISAMOTO clearly is in direct contact with a sidewall of the third gate trench (TR, right). (FIG. 2).
Applicant’s arguments with respect to the amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ANH D MAI/Primary Examiner, Art Unit 2893