DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I in the reply filed on 09/14/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected group, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 09/14/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Jang et al. (US20230187329A1).
Regarding claim 1, Figs.3A and 3B of Jang teach a semiconductor package, comprising:
a first die 22 (para.0032) and a second die 21 (para.0032); and
an interconnect structure 100 (para.0032) attached to the first die 22 and the second die 21, wherein the interconnect structure 100 comprises: a semiconductor substrate 110 (para.0036) comprising a first side S2 (para.0037) and a second side S1 (para.0040) opposite to the first side S2, the first side S2 being closer to the first die 22 and the second die 21 than the second side S1;
a routing structure 130 (para.0039) disposed at the first side S2 of the semiconductor substrate 110, wherein the first die 22 is electrically coupled to the second die 21 through at least the routing structure 130;
a metallization pattern 101/143-1 (para.0036, para 50; Fig. 3B -where Fig. 3B is an enlargement of portion of Fig. 3A) disposed at the second side S1 of the semiconductor substrate 110, wherein the metallization pattern 101/143-1 comprises a first metallization feature 101 (para.0036) and a second metallization feature 143-1 (para.0049), wherein the second metallization feature 143-1 is electrically isolated (para 0049, where features 143-1 are dummy patten not used in device operation or function); and
a through via 120 (para.0053) extending through the semiconductor substrate 110 and electrically coupling the routing structure 130 to the first metallization feature 101.
Regarding claim 6, Jang further teaches the semiconductor package of claim 1, wherein the second metallization feature 143-1 (para.0049) is a matrix of strips (para.0049, strips of first dummy patterns 143-1 as depicted in Fig.3B) in a top view.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 and 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US20230187329A1) in view of Chen et al. (US20190131273A1).
Regarding claim 2, Jang does not teach wherein the semiconductor package of claim 1, further comprising a first encapsulant laterally surrounding the interconnect structure and the through via.
Fig.4 of Chen teaches wherein a first encapsulation layer E1 encapsulates the sidewalls of the first and second semiconductor chips 101 and 201; wherein the first and second semiconductor chips 101 and 201 act as interconnect structures. The first encapsulation layer E1 also surrounds through integrated fan-out vias TIV (para.0052).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jang’s device to include Chen’s first encapsulation layer E1 in order to encapsulate or surround the sidewalls of substrate 100 and through-via 120 of Jang as taught by Chen (Chen, [para.0021]).
Regarding claim 3, the combination of Jang and Chen (see Chen) further teaches the semiconductor package of claim 2, wherein top surfaces of the interconnect structure 101/201 (para.0052), the first encapsulant E1 (para.0052), and the through via TIV (para.0052) are level.
Regarding claim 4, Jang does not teach wherein the semiconductor package of claim 3, further comprising a redistribution structure over the interconnect structure and the first encapsulant, wherein the redistribution structure is between the first die and the interconnect structure.
Fig.4 of Chen teaches wherein a second redistribution layer structure RDL2 is formed over the first encapsulation layer E1 and first semiconductor chips 101 and the second semiconductor chips 201 (wherein chips 101 and 201 correspond to interconnection structure); the second redistribution layer structure RDL2 is formed between third and fourth semiconductor chips 300 and 400 and the first and second semiconductor chips 101 and 201 (para.0046-0047).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jang’s device to have Chen’s second redistribution layer structure RDL2 formed between substrate 100 and chips 20 because redistribution layer structures are known to provide electrical pathways that connect the die to the package leads, ball arrays, or PCBs, handling both signal and power distribution and thus can provide electrical pathway between substrate 100 and chips 20.
Regarding claim 21, Figs.3A and 3B of Jang teach a semiconductor package, comprising:
a first metallization feature 101 (para.0036) extending along a horizontal plane (wherein horizontal plane is along X-direction of substrate 110);
a through via 120 (para.0053) connected to the first metallization feature 101 and extending vertically from the horizontal plane;
an interconnect structure 100 (para.0032) laterally displaced from the through via 120 along the horizontal plane, the interconnect structure 100 comprising a semiconductor substrate 110 (para.0036), a routing structure 130 (para.0039) at a first side S2 (para.0037) of the semiconductor substrate 110, and a second metallization feature at a second side S1 (para.0040) of the semiconductor substrate 110 opposite to the first side, wherein the first side S2 of the semiconductor substrate 110 faces away from the horizontal plane.
Jang does not teach a first encapsulant around the first metallization feature, the interconnect structure, and the through via, wherein respective top surfaces of the interconnect structure and the through via are free from the first encapsulant; and
a redistribution structure at the second side of the semiconductor substrate, wherein the redistribution structure is in physical contact with the second metallization feature.
Fig.4 of Chen teaches wherein a first encapsulation layer E1 encapsulates the sidewalls of the first and second semiconductor chips 101 and 201; wherein the first and second semiconductor chips 101 and 201 act as interconnect structures. The first encapsulation layer E1 also surrounds through integrated fan-out vias TIV (para.0052). Fig.4 of Chen also teaches a first redistribution layer structure RDL1 that includes a plurality of redistribution layers 104 embedded by a plurality of polymer layers 102.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jang’s device to include Chen’s first encapsulation layer E1 and first redistribution layer structure RDL1 because the first encapsulation layer E1 helps to encapsulate the sidewalls of substrate 100 and the through-via 120 and the first redistribution layer structure RDL1 is included because redistribution layer structures are known to provide electrical pathways that connect the die to the package leads, ball arrays, or PCBs, handling both signal and power distribution.
Regarding claim 22, Jang further teaches the semiconductor package of claim 21, further comprising an alignment mark 141 (Fig.5B, para.0049, wherein the first embossed pattern 141 may be formed using the first dummy pattern 143-1 without an additional process for forming the first embossed pattern 141) extending along the horizontal plane (wherein horizontal plane is along X-direction of substrate 110).
Regarding claim 23, Jang further teaches the semiconductor package of claim 21, wherein the interconnect structure further comprises a second alignment mark 142 (Fig.5B, para.0052, wherein the second embossed pattern 142 may have a curved shape corresponding or conforming to a surface of the second dummy pattern 143-2. A line width of the second dummy pattern 143-2) on the second side S1 (para.0040) of the semiconductor substrate 110 (para.0036).
Regarding claim 24, Jang further teaches the semiconductor package of claim 22, wherein the alignment mark is a matrix of strips (pads 101 act as matrix strips) in a top view.
Regarding claim 25, Jang further teaches the semiconductor package of claim 23, wherein the second alignment mark 141 (Fig.3B, para.0049) is a matrix of strips (para.0049, strips of first dummy patterns 143-1 as depicted in Fig.3B) in a top view.
Regarding claim 26, Jang does not teach wherein the interconnect structure further comprises a through via extending through the semiconductor substrate and electrically coupling the routing structure to the first metallization feature.
Fig.4 of Chen, teaches wherein first and second semiconductor chips 101 and 201 (wherein chips 101 and 201 correspond to interconnection structure) comprise through silicon vias TSV1 and TSV2 which provide electrical connection between pads 100b/200b and pads 100e/200e (para.0039).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jang’s device to include the through vias of Chen in order to provide more electrical connection between the pads and the interconnection structure.
Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US20210366833A1) in view of Jang et al. (US20230187329A1).
Regarding claim 8, Figs.5F-5G of Huang teaches a semiconductor package, comprising:
a first redistribution structure 830 (para.0058) comprising a conductive element (see Fig.5G);
an interconnect structure 400 (para.0043) over the first redistribution structure 830, wherein the interconnect structure 400 comprises:
a semiconductor substrate 410 (para.0057) having a first side and a second side, the second side being opposite to the first side, the second side facing the first redistribution structure 830;
a routing structure 420 (Figs.5D, para.0043) at the first side of the semiconductor substrate 410; and
a metallization pattern 460 (Fig.5E, para.0052) at the second side of the semiconductor substrate 410, wherein the metallization pattern 460 comprises a first metallization feature, wherein the first metallization feature is in physical contact with the conductive element of the first redistribution structure 830;
a first encapsulant 820 (para.0058) over the first redistribution structure 830 and laterally surrounding the interconnect structure 400;
a second redistribution structure 800 (para.0058) over the interconnect structure 400 and the first encapsulant 820; and a semiconductor die 700 (para.0051) over the second redistribution structure 800.
Huang does not teach wherein the metallization pattern comprises a second metallization feature; wherein the second metallization feature is electrically isolated.
Fig.3B of Jang teaches a semiconductor package 1000B that includes a first dummy pattern 143-1 (which corresponds to second metallization) corresponding to the first embossed pattern 141 of FIG. 1B; wherein the dummy patterns may not be used in device operation or function (para.0049). The plurality of dummy patterns 143-1 and/or 143-2 may be electrically insulated from the plurality of bump pads 101 (para.0053).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Huang’s device to include Jang’s dummy patterns 143-1/143-2 for the purpose of alignment purposes as depicted in Fig.5B of Jang wherein the first and second embossed patterns 141 and 142 may be provided in such a manner that a plurality of bar structures surround exteriors or perimeters of a first region R1 and a plurality of bump pads 101 (para.0056, [Jang]).
Regarding claim 9, Huang further teaches the semiconductor package of claim 8, wherein the interconnect structure 400 (para.0043) further comprises a through via 440 (Fig.5E, para.0044) extending through the semiconductor substrate 410 (para.0043) and electrically coupling the routing structure 420 (Figs.5D, para.0043) to the first metallization feature 460 (Fig.5E, para.0052).
Regarding claim 10, Huang further teaches the semiconductor package of claim 9, wherein the interconnect structure 400 (para.0043) further comprises an insulating layer 450 (para.0052) disposed between the metallization pattern 460 (Fig.5E, para.0052) and the semiconductor substrate 410 (para.0043), wherein the insulating layer 450 laterally surrounds the through via 440 (Fig.5E, para.0044).
Regarding claim 11, the combination of Huang and Jang further teaches the semiconductor package of claim 10, wherein the insulating layer 450 (para.0052) is in physical contact with the first metallization feature 460 (Fig.5E, para.0052) and the second metallization feature 143-1 (Jang, Fig.4B, para.0049).
Regarding claim 12, Huang further teaches the semiconductor package of claim 8, wherein the routing structure 420 (Figs.5D, para.0043) comprises curved sidewalls.
Regarding claim 13, the combination of Huang and Jang further teaches the semiconductor package of claim 12, wherein the interconnect structure 400 (para.0043) further comprises a second encapsulant 600a (Fig.5E, para.0051) laterally surrounding the first metallization feature 460 (Fig.5E, para.0052) and the second metallization feature 143-1 (Jang, Fig.4B, para.0049), wherein the second encapsulant 600a is in physical contact with the curved sidewalls of the routing structure 420 (Figs.5D, para.0043).
Regarding claim 14, Huang further teaches the semiconductor package of claim 13, wherein a sidewall of the semiconductor substrate 410 (para.0057) and a sidewall of the second encapsulant 600a (Fig.5E, para.0057) are laterally coterminous.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US20230187329A1) in view of Tsai et al. (US20220359468A1).
Regarding claim 5, Jang does not teach wherein the first metallization feature and the second metallization feature have a same height.
Fig.1F of Tsai teaches conductive vias 500 are formed on the interconnection structure 400 (para.0023); wherein first metallization feature and the second metallization features are depicted by the annotated Fig.1F to have the same height.
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451
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the conductive vias 500 of Tsai in the teachings of Jang so that they can be used for electrical testing purposes (Tsai, [para.0024]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US20230187329A1) in view of Huang et al. (US20210366833A1).
Regarding claim 7, Jang does not teach wherein the routing structure has curved sidewalls.
Fig.1E of Huang teaches a semiconductor die 100 that includes interconnect structure 120 with curved sidewalls formed as of grooves G1 (para.0019).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the sidewalls of Jang’s interconnection region, as taught by Huang, in order to protect the interconnection region from being damaged during wafer sawing process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/TUCKER J WRIGHT/Primary Examiner, Art Unit 2891
Prosecution Insights