CTNF 18/738,930 CTNF 89731 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE VERTICAL TRANSISTOR Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-5, 7 and 10 is/are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Sasaki [US PGPUB 20160233251] . Regarding claim 1, Sasaki teaches a semiconductor device comprising: a transistor (510, Para 69); and a first insulating layer (130, Para 50), wherein the transistor comprises a first conductive layer (120, Para 51), a second conductive layer (145, Para 51), a third conductive layer (160, Para 51), a semiconductor layer (140, Para 51), and a second insulating layer (150, Para 51), wherein the first insulating layer comprises a first layer (Para 63) and a second layer (Para 63, wherein layer 130 is a stack of layers, where “over” can be interpreted as over a top surface or over a bottom surface) over the first layer (Fig. 15), wherein the first insulating layer is over the first conductive layer (Fig. 15) and comprises a first opening (region in which material is formed to contact layer 120, Fig. 15) reaching the first conductive layer (Fig. 15), wherein the second conductive layer is over the second layer (Fig. 15), wherein the semiconductor layer comprises a part in contact with the first conductive layer (Fig. 15), a part in contact with the second conductive layer (Fig. 15), and a part in contact with a side surface of the first layer inside the first opening (Fig. 115C), wherein the second insulating layer covers the semiconductor layer in the first opening (Fig. 15), wherein the third conductive layer covers the second insulating layer in the first opening (Fig. 15), wherein the first insulating layer comprises a second opening (region in which materials 150/170/182 are formed, Fig. 15) at a position different from the first opening (Fig. 15), wherein the second insulating layer comprises a part in contact with the first layer inside the second opening (Fig. 15), wherein the first layer comprises an oxide insulating film (Para 63), and wherein the second layer comprises an insulating film having an oxygen barrier property (wherein the second layer is silicon nitride, Para 63). Regarding claim 2, Sasaki teaches a semiconductor device wherein the second opening is at a position not overlapping with the second conductive layer in a plan view (Fig. 15). Regarding claim 3, Sasaki teaches a semiconductor device wherein the second opening comprises a part overlapping with the third conductive layer (Fig. 15, i.e., overlap along the horizontal plane). Regarding claim 4, Sasaki teaches a semiconductor device wherein the second opening comprises a part overlapping with the first conductive layer (Fig. 15). Regarding claim 5, Sasaki teaches a semiconductor device wherein the second opening penetrates the second layer and reaches the first layer (Fig. 15, it should be noted that the claim is drawn to a device, “opening penetrates the second layer and reaches the first layer” is understood as opening that extends through both the second layer and the first layer –moreover, as noted, no limitation defines the point of penetration). Regarding claim 7, Sasaki teaches a semiconductor device wherein the second opening penetrates the second layer and the first layer, and wherein the second insulating layer is in contact with a side surface of the first insulating layer inside the second opening (Fig. 15). Regarding claim 10, Sasaki teaches a semiconductor device wherein the first layer comprises silicon oxide, and wherein the second layer comprises silicon nitride or aluminum oxide (Para 63) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Takeda et al. [US PGPUB 20160276492] (hereinafter Takeda) . Regarding claim 8, Sasaki teaches a semiconductor device comprising the limitation of claim 1 upon which it depends. Sasaki does not specifically disclose wherein the first insulating layer comprises a third layer below the first layer, and wherein the second opening penetrates the second layer and the first layer and reaches the third layer. Referring to the invention of Takeda, Takeda teaches forming an insulation layer 50 around oxide semiconductor layer 40, and wherein the insulation layer is a stacked layer of silicon oxide film, an aluminum oxide film and a silicon oxide film. In view of such teaching by Takeda, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Sasaki comprise the invention of Takeda to suppress the degradation in performance of the oxide semiconductor layer and block hydrogen and oxygen generated in the device (Takeda, Para 50). A person having ordinary skills in the art will understand that the amendment of Sasaki’s invention with the teachings of Takeda will read on the claimed limitation. Regarding claim 9, Sasaki teaches a semiconductor device comprising the limitation of claim 1 upon which it depends. Sasaki does not specifically disclose wherein the first insulating layer comprises a third layer below the first layer, and wherein the second opening penetrates the second layer, the first layer, and the third layer. Referring to the invention of Takeda, Takeda teaches forming an insulation layer 50 around oxide semiconductor layer 40, and wherein the insulation layer is a stacked layer of silicon oxide film, an aluminum oxide film and a silicon oxide film. In view of such teaching by Takeda, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Sasaki comprise the invention of Takeda to suppress the degradation in performance of the oxide semiconductor layer and block hydrogen and oxygen generated in the device (Takeda, Para 50). A person having ordinary skills in the art will understand that the amendment of Sasaki’s invention with the teachings of Takeda will read on the claimed limitation . 07-21-aia AIA Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Lin US PGPUB 20230103531] . Regarding claim 11, Sasaki teaches a semiconductor device comprising the limitation of claim 1 upon which it depends. Sasaki does not specifically disclose wherein a shortest distance between the first opening and the second opening is greater than or equal to 0.1 µm and less than or equal to 100 µm. Referring to the invention of Lin, Lin teaches an exemplary structure of have contacts formed openings close to one another on a substrate, wherein the distance between the openings is, for instance, about 3 micrometers (μm) to 15 μm (3 μm<D 1 <15 μm), wherein the distance should however not be construed as a limitation. The distance being the minimum distance measured in the openings (Para 37). In view of such teaching by Lin, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Sasaki comprise the teachings of Lin at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim 12 is allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 The following is a statement of reasons for the indication of allowable subject matter Claim 12 is allowable because all prior arts of record and related prior arts not of record either singularly or in combination fail to anticipate or render obvious a method for manufacturing a semiconductor device, comprising the steps of: etching a part of the semiconductor film to expose the second opening; forming an insulating layer covering the semiconductor film and the second opening; and forming, over the insulating layer, a third conductive layer overlapping with the semiconductor layer, in combination with the rest of claim limitations as claimed and defined by the Applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISMAIL A MUSE whose telephone number is (571)272-1470. The examiner can normally be reached Monday - Friday 8:00 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571)270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ISMAIL A MUSE/ Primary Examiner, Art Unit 2812 Application/Control Number: 18/738,930 Page 2 Art Unit: 2812 Application/Control Number: 18/738,930 Page 3 Art Unit: 2812 Application/Control Number: 18/738,930 Page 4 Art Unit: 2812 Application/Control Number: 18/738,930 Page 5 Art Unit: 2812 Application/Control Number: 18/738,930 Page 6 Art Unit: 2812 Application/Control Number: 18/738,930 Page 7 Art Unit: 2812
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