Prosecution Insights
Last updated: July 17, 2026
Application No. 18/738,986

DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §103
Filed
Jun 10, 2024
Priority
Oct 26, 2023 — RE 10-2023-0144315
Examiner
GREWAL, HEIM KIRIN
Art Unit
Tech Center
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
1y 4m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
30 granted / 34 resolved
+28.2% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
25 currently pending
Career history
59
Total Applications
across all art units

Statute-Specific Performance

§103
92.9%
+52.9% vs TC avg
§102
6.6%
-33.4% vs TC avg
§112
0.6%
-39.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 34 resolved cases

Office Action

§103
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims The following is in response to the communication filed 6/10/2024. Claims 1-20 are currently pending. Claims 1-20 have been examined. Priority Applicant' s claim for the benefit of prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to Korean Patent Application No. 10- 2023-0144315, filed on October 26, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) submitted on 6/10/2024 and 12/03/2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: DISPLAY DEVICE INCLUDING SLOPED SURFACE FOR LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-2, 5-6, 10-13, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. US 20230120937 A1 (hereinafter Hong) in view of Han et al. US 20220262873 A1 (hereinafter Han). The following annotated drawing of Hong Fig. 2 will be used in discussion. PNG media_image1.png 668 979 media_image1.png Greyscale Regarding claim 1, Hong discloses: A display device (Hong, Abstract, Fig. 2, display device 100) comprising: a substrate (substrate 110) including a display area ([0072] emission area EA, including REA, GEA, and BEA) and a non-display area; (non-emission area NEA) a thin film transistor (transistor 120) on the substrate; (substrate 110) a planarization layer (first overcoating layer 130) on the thin film transistor; (transistor 120) a via layer (second overcoating 150) on the planarization layer, (first overcoating layer 130) having a recess (annotated Fig. 2, recess) in the display area (second overcoating 150)) ….; a sub-pixel (light emitting element 160) including a first electrode, ( first electrode 161) an organic light emitting layer, (organic layer 162) and a second electrode (second electrode 163) corresponding to the recess; (See Fig.2 for the light emitting element 160 being within the recess.) and a pixel definition layer (banks 170) defining the sub-pixel (light emitting element 160) on the via layer, (second overcoating 150) wherein the first electrode ( first electrode 161) is electrically connected to the thin film transistor ([0063], the first electrode is electrically connected to the source electrode of the transistor 120.) and includes an inclined electrode arranged along a sloped surface of the recess. (See Fig. 2, for light emitting element 160 being arranged along the sloped surface of the recess.) Hong does not appear to disclose: an alignment mark in the non-display area. Han, which discloses a display device and method of preparation (Han, Abstract), discloses: an alignment mark (Fig. 27, alignment marks 2200) in the non-display area. ([0138], the alignment marks 2200 are in the non-display area 22 and are formed simultaneously in the film layers so that they can be used for the purpose of aligning different layers.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong to have an alignment mark in the non-display area as taught by Han for purposes of aligning different layers during processing. Regarding claim 2, Hong and Han disclose all the elements of claim 1. Hong further discloses: the first electrode (light emitting element 160) further comprises a lower electrode (annotated Fig. 2, lower electrode 160-1) extending from a bottom end of the inclined electrode (inclined electrode 160-2) and in the recess, (See Fig. 2) and an upper electrode (annotated Fig. 2., upper electrode 160-3) extending from a top end of the inclined electrode (inclined electrode 160-2) and on a top surface of the via layer. (second overcoating 150) Regarding claim 5, Hong and Han disclose all the elements of claim 2. Hong further discloses: the organic light emitting layer (organic layer 162) overlaps the lower electrode,(annotated Fig. 2, lower electrode 160-1) the inclined electrode, (inclined electrode 160-2) and the upper electrode (upper electrode 160-3). Regarding claim 6, Hong and Han disclose all the elements of claim 1. Hong further discloses: the pixel defining layer (banks 170) directly contacts a top surface of the via layer.(Fig. 2, the top surface of the second overcoating layer 150 contacts the banks 170.) Regarding claim 10, Hong and Han disclose all the elements of claim 1. Hong further discloses: a thin film encapsulation layer (Fig. 2, encapsulation unit 180) on the sub-pixel (light emitting element 160) and the pixel defining layer (banks 170). Regarding claim 11, Hong discloses: A method of manufacturing display device (Hong, Abstract, Fig. 2, display device 100) comprising: forming a planarization layer (first overcoating layer 130) on a substrate (substrate 110) having a thin film transistor; (transistor 120) forming an organic layer (annotated Fig. 2, organic layer) on the planarization layer; (first overcoating layer 130) patterning the organic layer (organic layer) to form a via layer (second overcoating 150) having a recess (See annotated Fig. 2, recess)….; forming a first electrode ( first electrode 161) electrically connected to the thin film transistor ([0063], the first electrode is electrically connected to the source electrode of the transistor 120.) and including an inclined electrode arranged along a sloped surface of the recess; and (See Fig. 2, for light emitting element 160 being arranged along the sloped surface of the recess.) forming a pixel defining layer (banks 170) exposing at least a portion of the first electrode (first electrode 161) on the via layer (second overcoating 150) …. Hong does not appear to disclose: an alignment mark, or forming a pixel defining layer … using the alignment marks. Han, which discloses a display device and method of preparation (Han, Abstract), discloses: an alignment mark (Fig. 27, alignment marks 2200, forming a pixel defining layer … using the alignment marks. [0138], (the alignment marks 2200 are in the non-display area 22 and are formed simultaneously in the film layers so that they can be used for the purpose of aligning different layers. Therefore, openings in the pixel defining layer would be aligned using the alignment marks. ) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong to have an alignment mark in the non-display area as taught by Han for purposes of aligning different layers during processing. 12. The method of claim 11, further comprising: Hong further discloses: forming a lower electrode (annotated Fig. 2, lower electrode 160-1) extending from a bottom end of the inclined electrode (inclined electrode 160-2) and in the recess, (See Fig. 2) and an upper electrode (annotated Fig. 2., upper electrode 160-3) extending from a top end of the inclined electrode (inclined electrode 160-2) and on a top surface of the via layer (annotated Fig. 2., upper electrode 160-3) in forming the first electrode. (light emitting element 160) Regarding claim 13, Hong and Han disclose all the elements of claim 11. forming an organic light emitting layer (organic layer 162) on a first electrode ( first electrode 161) exposed by the pixel defining layer; (Fig. 2, the exposed area between the banks 170) and forming a second electrode (second electrode 163) on the organic light emitting layer. (organic layer 162) Regarding claim 16, Hong and Ha disclose all the elements of claim 11. Hong further discloses: the pixel defining layer (banks 170) is formed to be in direct contact with a top surface of the via layer. (Fig. 2, the top surface of the second overcoating layer 150 contacts the banks 170.) Regarding claim 20, Hong and Han disclose all the elements of claim 13. Hong further discloses: forming a thin film encapsulation layer (Fig. 2, encapsulation unit 180) on the second electrode. (second electrode 163) Claims 3-4 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hong and Han as applied to claims 1 and 11 above, and further in view of Yan US 20240284722 A1 (hereinafter Yan). The following annotated drawing of Yan Fig. 1 will be used in discussion. PNG media_image2.png 600 895 media_image2.png Greyscale Regarding claim 3, Hong and Han disclose all the elements of claim 2. Hong further discloses: wherein the upper electrode (annotated Fig. 2, upper electrode 160-3) comprises a concealed portion (concealed portion 160a) that overlaps the pixel defining layer (banks 170) and Hong and Han do not appear to disclose: an exposed portion that does not overlap the pixel defining layer. Yan, which teaches an OLED display panel (Yan, Abstract and Background), disclose: the upper electrode (Yan, annotated Fig. 1, the first electrode upper electrode 151_3) comprises a concealed portion (concealed portion 16a) that overlaps the pixel defining layer (pixel definition layer 16) and an exposed portion (exposed portion 16b) that does not overlap the pixel defining layer. (pixel definition layer 16) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong and Han to have an exposed portion that does not overlap the pixel defining layer as taught by Yan for purposes of reflecting the display light repeatedly over the flat portion and improving the light-emitting efficiency of the light-emitting device. (Yan, [0044].) Regarding claim 4 , Hong, Han, and Yang disclose all the elements of claim 3. Although Hong, Han, and Yan do not appear to teach that the exposed portion has a length in a range of 1 micrometers (μm) to 2 μm, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions does not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)). In this case, nothing on the record indicates that the claimed thickness of exposed portion would cause the structure to operate differently. Regarding claim 14, Hong and Han disclose all the elements of claim 12. Hong further discloses: the pixel defining layer (banks 170) exposes the lower electrode (annotated Fig. 2, lower electrode 160-1) …. and overlaps at least a portion of the upper electrode. (upper electrode 160-3) Hong does not appear to disclose the pixel defining layer exposes “the inclined electrode.” Yan, which teaches an OLED display panel (Yan, Abstract and Background), disclose: the pixel defining layer (pixel definition layer 16) exposes the lower electrode (lower electrode 151_1) and the inclined electrode (inclined 151_2) and overlaps at least a portion of the upper electrode.( upper electrode 151_3) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong and Han to have an exposed portion that does not overlap the pixel defining layer as taught by Yan for purposes of reflecting the display light repeatedly over the flat portion and improving the light-emitting efficiency of the light-emitting device. (Yan, [0044].) Regarding claim 15, Hong, Han and Yan disclose all the elements of claim 14. Hong further discloses: the upper electrode (annotated Fig. 2, upper electrode 160-3) comprises a concealed portion (concealed portion 160a) that overlaps the pixel defining layer (banks 170) and Yan further discloses: the upper electrode (Yan, Fig. 1, the first electrode upper electrode 151_3) comprises a concealed portion (concealed portion 16a) that overlaps the pixel defining layer (pixel definition layer 16) and an exposed portion (exposed portion 16b) that does not overlap the pixel defining layer. (pixel definition layer 16) Although Hong, Han and Yan do not appear to teach that the exposed portion has a length in a range of 1 micrometers (μm) to 2 μm, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions does not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)). In this case, nothing on the record indicates that the claimed thickness of exposed portion would cause the structure to operate differently. Claims 7-9 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hong and Han as applied to claim 1 above, and further in view of Ring et al. US 20190271810 A1 (hereinafter Ring). Regarding claim 7, Hong and Han disclose all the elements of claim 1. Han does not specifically discloses: the alignment mark is made of a same material as the via layer. Ring, which generally teaches optical planar waveguides (Ring, Abstract) and specifically teaches that alignment marks are used for optical, electrical and optoelectrical devices for accurate placement of layers in the device ([0157] and [0158]), discloses: the alignment mark is made of a same material as the via layer. (Ring, [0157], The alignment mark can be made by patterning the mark into the layer as an etched feature. Therefore the alignment would be made of the same material as the layer in which it is in.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong and Han to have the alignment mark is made of a same material as the via layer as taught by Ring for purposes of aligning different layers during processing. Regarding claim 8, Hong and Han disclose all the elements of claim 1. Hong and Han do not specifically discloses: the alignment mark is formed in an engraved pattern in which a portion of a top surface of the via layer is recessed. Ring, which generally teaches optical planar waveguides (Ring, Abstract) and specifically teaches that alignment marks are used for optical, electrical and optoelectrical devices for accurate placement of layers in the device ([0157] and [0158]), discloses: the alignment mark is formed in an engraved pattern in which a portion of a top surface of the via layer is recessed. (Ring, [0157], The alignment mark can be made by patterning the mark into the layer as an etched feature. Therefore the alignment would be made of the same material as the layer in which it is in.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong and Han to have the alignment mark is formed in an engraved pattern in which a portion of a top surface of the via layer is recessed as taught by Ring for purposes of aligning different layers during processing. Regarding claim 9, Hong, Han and Ring disclose all the elements of claim 8. Ring further disclose: the alignment mark comprises an ink that fills the engraved pattern, and the ink has a different color to the top surface of the via layer. ([0157], the patterned feature include an ink mark which is either a coloration or discoloration mark in the layer on the substrate.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong, Han, and Ring to have an ink that fills the engraved pattern, and the ink has a different color to the top surface of the via layer as taught by Ring for purposes of providing optical contrast for the alignment mark. (Ring, [0157]) Regarding claim 17. Hong and Han disclose all the elements of claim 11. Hong and Han do not specifically discloses: alignment mark is made of a same material as the via layer. Ring, which generally teaches optical planar waveguides (Ring, Abstract) and specifically teaches that alignment marks are used for optical, electrical and optoelectrical devices for accurate placement of layers in the device ([0157] and [0158]), discloses: the alignment mark is made of a same material as the via layer. (Ring, [0157], The alignment mark can be made by patterning the mark into the layer as an etched feature. Therefore the alignment would be made of the same material as the layer in which it is in.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong and Han to have the alignment mark is made of a same material as the via layer as taught by Ring for purposes of aligning different layers during processing. Regarding claim 18, Hong and Han disclose all the elements of claim 11. Hong and Han do not specifically discloses: Ring, which generally teaches optical planar waveguides (Ring, Abstract) and specifically teaches that alignment marks are used for optical, electrical and optoelectrical devices for accurate placement of layers in the device ([0157] and [0158]), discloses: the alignment mark is formed in an engraved pattern in which a portion of the top surface of the via layer is recessed. Ring, [0157], The alignment mark can be made by patterning the mark into the layer as an etched feature. Therefore the alignment would be made of the same material as the layer in which it is in.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong and Han to have the alignment mark is formed in an engraved pattern in which a portion of a top surface of the via layer is recessed as taught by Ring for purposes of aligning different layers during processing. Regarding claim 19, Hong, Han and Ring disclose all the elements of claim 18. the alignment mark comprises an ink that fills the engraved pattern, wherein the ink has a different color to the top surface of the via layer. ([0157], the patterned feature include an ink mark which is either a coloration or discoloration mark in the layer on the substrate.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hong, Han, and Ring to have an ink that fills the engraved pattern, and the ink has a different color to the top surface of the via layer as taught by Ring for purposes of providing optical contrast for the alignment mark. (Ring, [0157]) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HEIM KIRIN GREWAL/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jun 10, 2024
Application Filed
Jun 26, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
88%
With Interview (+0.0%)
3y 6m (~1y 4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 34 resolved cases by this examiner. Grant probability derived from career allowance rate.

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