Prosecution Insights
Last updated: August 17, 2026
Application No. 18/739,261

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §103
Filed
Jun 10, 2024
Priority
Jul 02, 2021 — CN 202110749340.4 +1 more
Examiner
KOO, LAMONT B
Art Unit
Tech Center
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
447 granted / 555 resolved
+20.5% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
32 currently pending
Career history
607
Total Applications
across all art units

Statute-Specific Performance

§103
65.3%
+25.3% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 555 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2015/0021683) (hereafter Xie), in view of Tang et al. (US 2021/0074829) (hereafter Tang). Regarding claim 1, Xie discloses a method for fabricating a semiconductor device, comprising: forming a metal gate (“one or more metal layers” and “bulk conductive material layer” in paragraph 0038) on a substrate 102 (Fig. 3C, paragraph 0034), a spacer 112 (Fig. 3C, paragraph 0035) around the metal gate 120 (Fig. 3C), and a first interlayer dielectric (ILD) layer 114 (Fig. 3C, paragraph 0035) around the spacer 112 (Fig. 3C); and forming a second ILD layer 168 (Fig. 4H, paragraph 0056) on the metal gate (“one or more metal layers” and “bulk conductive material layer” in paragraph 0038) and the first ILD layer 114 (Fig. 4H). Xie does not disclose performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion; and performing a cleaning process to remove the first top portion. Tang discloses performing a plasma treatment process (“ion implantation process” in paragraph 0069) to transform the spacer 203 (Fig. 7, paragraph 0068) into a first bottom portion (element number is not shown in Fig. 8 but see 203 in Fig. 8) and a first top portion 207 (Fig. 8, paragraph 0068); and performing a cleaning process (see Fig. 10 and paragraph 0075) to remove the first top portion 207 (Fig. 8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie to include performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion; and performing a cleaning process to remove the first top portion, as taught by Tang, since the modified isolation layer (Tang, paragraph 0070) may have an etching rate less than the dummy gate dielectric layer, such that when removing the dummy gate dielectric layer, the modified isolation layer may be etched to a lesser extent and the height (Tang, paragraph 0070) of the isolation layer may determine the effective height of a subsequently formed gate structure. Therefore, the subsequently formed gate structure (Tang, paragraph 0070) may have a substantially large height, and the electric field control capability of the gate structure may be substantially strong, thereby improving the performance of the semiconductor structure. Regarding claim 10, Xie in view of Tang discloses the method of claim 1, however Xie does not disclose an oxygen concentration in the first bottom portion is lower than an oxygen concentration in the first top portion. Tang discloses an oxygen concentration in the first bottom portion (element number is not shown in Fig. 8 but see 203 in Fig. 8) is lower (see Figs. 7-8 and paragraph 0070, wherein the implanted ion may include oxygen ion such that an oxygen concentration of 203 is lower than an oxygen concentration of 207) than an oxygen concentration in the first top portion 207 (Fig. 8, paragraph 0068). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie to include an oxygen concentration in the first bottom portion is lower than an oxygen concentration in the first top portion, as taught by Tang, since the modified isolation layer (Tang, paragraph 0070) may have an etching rate less than the dummy gate dielectric layer, such that when removing the dummy gate dielectric layer, the modified isolation layer may be etched to a lesser extent and the height (Tang, paragraph 0070) of the isolation layer may determine the effective height of a subsequently formed gate structure. Therefore, the subsequently formed gate structure (Tang, paragraph 0070) may have a substantially large height, and the electric field control capability of the gate structure may be substantially strong, thereby improving the performance of the semiconductor structure. Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Xie, in view of Tang as applied to claim 1 above, and further in view of Fu et al. (US 2012/0139042) (hereafter Fu). Regarding claim 2, Xie further discloses the method of claim 1, further comprising: forming a gate structure 108 (Fig. 3A, paragraph 0035) on the substrate 102 (Fig. 3A), wherein the gate structure 108 (Fig. 3A) comprises a gate material layer 108 (Fig. 3A); forming the spacer 112 (Fig. 3A) around the gate structure 108 (Fig. 3A); forming a source/drain region 111 (Fig. 3A, paragraph 0043) adjacent to the spacer 112 (Fig. 3A); forming a contact etch stop layer (CESL) 113 (Fig. 3A, paragraph 0043) around the spacer 112 (Fig. 3A); forming the first interlayer dielectric (ILD) layer 114 (Fig. 3A) around the CESL 113 (Fig. 3A). Xie and Tang do not disclose removing the gate material layer and the spacer to form a first recess and a second recess; forming a work function metal layer in the first recess and the second recess; forming a low resistance metal layer on the work function metal layer; and planarizing the low resistance metal layer to form the metal gate. Fu discloses removing (see Figs. 5-6A, paragraphs 0018-0019) the gate material layer 106 (Fig. 5, paragraph 0018) and the spacer 114a (Fig. 5, paragraph 0018) to form a first recess 134 (Fig. 6A, paragraph 0019) and a second recess 132 (Fig. 6A, paragraph 0018); forming a work function metal layer 140 (Fig. 7, paragraph 0021) in the first recess 134 (Fig. 6A) and the second recess 132 (Fig. 6A); forming a low resistance metal layer 142 (Fig. 7, paragraph 0021) on the work function metal layer 140 (Fig. 7); and planarizing (see Fig. 8 and paragraph 0022, wherein “planarization process”) the low resistance metal layer 142 (Fig. 7) to form the metal gate 140 (Fig. 8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie in view of Tang to include performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion; and performing a cleaning process to remove the first top portion, as taught by Fu, since the work function metal layer 140 (Fu, Fig. 8, paragraph 0024) and the filling metal layer 142 (Fu, Fig. 8, paragraph 0024) are easily formed in the T-shaped gate trench 130 (Fu, Fig. 7, paragraph 0024) without forming any seam in the T-shaped gate trench 130 (Fu, Fig. 7, paragraph 0024), and thus the reliability of the T-shaped metal gate 150 (Fu, Fig. 8, paragraph 0024) is improved. Regarding claim 3, Xie in view of Tang and Fu discloses the method of claim 2, however Xie and Tang do not disclose removing the spacer and the CESL to form the second recess. Fu discloses removing (see Fig. 6A) the spacer 114a (Fig. 5, paragraph 0018) and the CESL 120 (Fig. 5, paragraph 0017) to form the second recess 132 (Fig. 6A, paragraph 0018). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie in view of Tang to include removing the spacer and the CESL to form the second recess, as taught by Fu, since the work function metal layer 140 (Fu, Fig. 8, paragraph 0024) and the filling metal layer 142 (Fu, Fig. 8, paragraph 0024) are easily formed in the T-shaped gate trench 130 (Fu, Fig. 7, paragraph 0024) without forming any seam in the T-shaped gate trench 130 (Fu, Fig. 7, paragraph 0024), and thus the reliability of the T-shaped metal gate 150 (Fu, Fig. 8, paragraph 0024) is improved. Regarding claim 4, Xie in view of Tang and Fu discloses the method of claim 2, however Xie and Tang do not disclose removing the spacer, the CESL, and the first ILD layer to form the second recess. Fu discloses removing (see Fig. 6A and paragraph 0017, wherein “planarization process”) the spacer 114a (Fig. 4, paragraph 0018), the CESL 120 (Fig. 4, paragraph 0017), and the first ILD layer 122 (Fig. 4, paragraph 0017) to form the second recess 132 (Fig. 6A, paragraph 0018). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie in view of Tang to include removing the spacer, the CESL, and the first ILD layer to form the second recess, as taught by Fu, since the work function metal layer 140 (Fu, Fig. 8, paragraph 0024) and the filling metal layer 142 (Fu, Fig. 8, paragraph 0024) are easily formed in the T-shaped gate trench 130 (Fu, Fig. 7, paragraph 0024) without forming any seam in the T-shaped gate trench 130 (Fu, Fig. 7, paragraph 0024), and thus the reliability of the T-shaped metal gate 150 (Fu, Fig. 8, paragraph 0024) is improved. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Xie, in view of Tang as applied to claim 1 above, and further in view of Lee et al. (US 2020/0105615) (hereafter Lee). Regarding claim 11, Xie in view of Tang discloses the method of claim 1, however Xie and Tang do not disclose the plasma treatment process comprises nitrous oxide (N2O). Lee discloses the plasma treatment process (“plasma treatment” in paragraph 0020) comprises nitrous oxide (N2O) (see “N.sub.2O” in paragraph 0020). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie in view of Tang to include the plasma treatment process comprises nitrous oxide (N2O), as taught by Lee, since a reshaping process is performed on the spacer 34 (Lee, Fig. 7B, paragraph 0020) to either reshape the spacer into a spacer 34′ (Lee, Fig. 8B, paragraph 0020) having a desired profile suitable for subsequently SiGe epitaxial growth, or further remove byproducts and chemical residues resulting from the spacer 34 (Lee, Fig. 7B, paragraph 0020). Allowable Subject Matter 1. Claims 5-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: 2. Claim 5 would be allowable because a prior art, Tang et al. (US 2021/0074829), discloses performing a plasma treatment process (“ion implantation process” in paragraph 0069) to transform the spacer 203 (Fig. 7, paragraph 0068) into a first bottom portion (element number is not shown in Fig. 8 but see 203 in Fig. 8) and a first top portion 207 (Fig. 8, paragraph 0068) but fails to disclose performing the plasma treatment process to transform the CESL into a second bottom portion and a second top portion. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a method for fabricating a semiconductor device, comprising: performing the plasma treatment process to transform the CESL into a second bottom portion and a second top portion in combination with other elements of the base claims 2 and 1. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claims 6-9 depend on claim 5. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /L.B.K/Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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Prosecution Timeline

Jun 10, 2024
Application Filed
Jul 23, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
86%
With Interview (+5.2%)
2y 6m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 555 resolved cases by this examiner. Grant probability derived from career allowance rate.

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