DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2015/0021683) (hereafter Xie).
Regarding claim 1, Xie discloses a semiconductor device, comprising:
a metal gate 120 (Fig. 4H, paragraph 0038) on a substrate 102 (Fig. 4H, paragraph 0034);
a spacer 112 (Fig. 4H, paragraph 0035) adjacent to the metal gate 120 (Fig. 4H);
a source/drain region 34 (Fig. 8, paragraph 0013) adjacent to the spacer 32 (Fig. 8);
a contact etch stop layer (CESL) (element number is not shown in Fig. 4H but see 113 in Fig. 4G, paragraph 0035) around the spacer 112 (Fig. 4H), wherein the spacer 112 (Fig. 4H) and the CESL (element number is not shown in Fig. 4H but see 113 in Fig. 4G) comprise different heights;
a first interlayer dielectric (ILD) layer 144 (Fig. 4H, paragraph 0047) around the CESL (element number is not shown in Fig. 4H but see 113 in Fig. 4G); and
a second ILD layer 168 (Fig. 4H, paragraph 0056) on the metal gate 120 (Fig. 4H) and the first ILD layer 114 (Fig. 4H), wherein part of the second ILD layer 168 (Fig. 4H) is lower than a top surface of the first ILD layer 114 (Fig. 4H).
Regarding claim 2, Xie further discloses the semiconductor device of claim 1, wherein a top surface (top surface of the CESL (element number is not shown in Fig. 4H but see 113 in Fig. 4G) contacting 114 in Fig. 4H) of the CESL (element number is not shown in Fig. 4H but see 113 in Fig. 4G) is lower than a top surface of the spacer 112 (Fig. 4H).
Regarding claim 3, Xie further discloses the semiconductor device of claim 1, wherein a top surface (top surface of the CESL (element number is not shown in Fig. 4H but see 113 in Fig. 4G) of the CESL (element number is not shown in Fig. 4H but see 113 in Fig. 4G) is lower than a top surface of the metal gate 120 (Fig. 4H).
Regarding claim 4, Xie further discloses the semiconductor device of claim 1, wherein a top surface of the spacer 112 (Fig. 4H) is lower than a top surface of the metal gate 120 (Fig. 4H).
Regarding claim 5, Xie further discloses the semiconductor device of claim 1, wherein the second ILD layer 168 (Fig. 4H) comprises: a bottom portion (bottom portion of 168 in Fig. 4H) between the metal gate 120 (Fig. 4H) and the first ILD layer 144 (Fig. 4H); and a top portion (top portion of 168 in Fig. 4H) on the metal gate 120 (Fig. 4H).
Regarding claim 6, Xie further discloses the semiconductor device of claim 5, wherein the bottom portion (bottom portion of 168 in Fig. 4H) contacts the spacer 112 (Fig. 4H) directly.
Regarding claim 7, Xie further discloses the semiconductor device of claim 5, wherein the bottom portion (bottom portion of 168 in Fig. 4H) contacts the CESL (element number is not shown in Fig. 4H but see 113 in Fig. 4G) directly.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Xie as applied to claim 5 above, and further in view of Lin et al. (US 2015/0118835) (hereafter Lin).
Regarding claim 8, Xie discloses the semiconductor device of claim 5, however Xie does not disclose a bottom surface of the bottom portion contacting the CESL is lower than a bottom surface of the bottom portion contacting the spacer.
Lin discloses a bottom surface of the bottom portion (bottom portion of 180 in Fig. 6, paragraph 0028) contacting the CESL 140 (Fig. 6, paragraph 0024) is lower than a bottom surface of the bottom portion (bottom portion of 180 in Fig. 6, paragraph 0028) contacting the spacer 130 (Fig. 6, paragraph 0024).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Xie to form a bottom surface of the bottom portion contacting the CESL is lower than a bottom surface of the bottom portion contacting the spacer, as taught by Lin, since the hard mask layer (Lin, paragraph 0007) subsequently formed to fill the recess obtains a width larger than a width of the metal gate such that short circuit (Lin, paragraph 0007) between the metal gate and the source/drain caused by contact plug misalign or contact plug shift is avoided.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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