Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 6-10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (Patent No.: US 11316024) (hereinafter Wang).
Re claim 1, Wang, FIGS. 1-4 teaches a memory cell, comprising:
a substrate (112);
a floating gate (120) disposed on the substrate;
a control gate (122) disposed on the floating gate;
a first dielectric layer (123) disposed between the floating gate (120) and the control gate (122);
an erase gate (130/122a) merged with the control gate (122) and disposed on a first sidewall of the floating gate (120);
a second dielectric layer (126) disposed between the floating gate (120) and the erase gate (130);
a select gate (128, col. 2, lines 13-32) disposed on an opposite second sidewall of the floating gate (120);
a spacer disposed between the select gate (128) and the control gate (130) and between the select gate (128) and the floating gate (120);
a source doping region (114) disposed in the substrate and adjacent to the first sidewall of the floating gate (120); and
a drain doping region (116) disposed in the substrate and adjacent to the select gate (128).
Re claim 6, Wang, FIG. 1 teaches the memory cell according to claim 1 further comprising:
a source line contact (S) disposed on the source doping region (114); and
a bit line contact (D) disposed on the drain doping region (116).
Re claim 7, Wang, FIG. 4 teaches the memory cell according to claim 6 further comprising:
an insulating layer (126) between the substrate (112) and the erase gate (130), wherein the insulating layer has a thickness that increases from the first sidewall of the floating gate (120) to the source line contact (middle top surface of 114).
Re claim 8, Wang, FIGS. 1-4 teaches the memory cell according to claim 1, wherein the erase gate (130/122a) is structurally integrated with the control gate (122a).
Re claim 9, Wang, FIGS. 5A-5F teaches the memory cell according to claim 1, wherein the erase gate (38a/38b), the control gate (34a/34b), the floating gate (14a/14b), and the select gate (18a/18b) are composed of polysilicon (col. 5, lines 127).
Re claim 10, Wang, FIGS. 1-4 teaches the memory cell according to claim 1 further comprising:
a select gate oxide layer (126) disposed between the select gate (128) and the substrate (112); and
a floating gate oxide layer (126) disposed between the floating gate (120) and the substrate (112).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Patent No.: US 11316024) (hereinafter Wang).
Re claim 2, Wang teaches the memory cell according to claim 1, wherein the first dielectric layer (16, col. 4, lines 8-12) is about the same the second dielectric layer (30, FIG. 5C → 5D).
Wang differs from the claim invention by not disclosing wherein the first dielectric layer is thicker than the second dielectric layer.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Re claim 3, Wang, FIGS. 5A-5F teaches the memory cell according to claim 2, wherein the first dielectric layer comprises an oxide-nitride-oxide (ONO) dielectric layer (16, col. 4, lines 8-12).
Re claim 4, Wang, FIGS. 5A-5F teaches the memory cell according to claim 3, wherein the second dielectric layer is a silicon oxide layer (30, col. 5, lines 5-10).
Re claim 5, Wang, FIGS. 1-4 teaches the memory cell according to claim 4, wherein the erase gate (130) partially overlaps with the source doping region (114).
Conclusion
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/TONY TRAN/Primary Examiner, Art Unit 2893
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